Datasheet

Datasheet, Volume 2 265
Processor Configuration Registers
2.21.1 VER_REG—Version Register
This register reports the architecture version supported. Backward compatibility for the
architecture is maintained with new revision numbers, allowing software to load
remapping hardware drivers written for prior architecture versions.
A8–ABh IEADDR_REG Invalidation Event Address Register 0000_0000h RW-L
AC–AFh IEUADDR_REG Invalidation Event Upper Address Register 0000_0000h RW-L
B0–B7h RSVD Reserved 0h RO
B8–BFh IRTA_REG
Interrupt Remapping Table Address Register 0000_0000_
0000_0000h
RW-L
C0–FFh RSVD Reserved 0h RO
100–107h IVA_REG
Invalidate Address Register 0000_0000_
0000_0000h
RW
108–10Fh IOTLB_REG
IOTLB Invalidate Register 0000_0000_
0000_0000h
RW, RO-V,
RW-V
110–1FFh RSVD Reserved 0h RO
200–207h RSVD
Reserved 0000_0000_
0000_0000h
ROS-V
208–20Fh RSVD
Reserved 0000_0000_
0000_0000h
ROS-V, RO,
RW1CS
210–FEFh RSVD Reserved 0h RO
FF0–FF3h RSVD
Reserved
0000_0000h
RO-KFW,
RW-KL,
RW-L, RO
Table 2-23. Default PEG/DMI VT-d Remapping Engine Register Address Map (Sheet 2 of 2)
Address
Offset
Register
Symbol
Register Name Reset Value Access
B/D/F/Type: 0/0/0/VC0PREMAP
Address Offset: 0–3h
Reset Value: 0000_0010h
Access: RO
Size: 32 bits
BIOS Optimal Default 000000h
Bit Attr
Reset
Value
RST/
PWR
Description
31:8 RO 0h Reserved
7:4 RO 0001b Uncore
Major Version number (MAX)
This field indicates supported architecture version.
3:0 RO 0000b Uncore
Minor Version number (MIN)
This field indicates supported architecture minor version.