Datasheet

Processor Configuration Registers
262 Datasheet, Volume 2
13:8 RWS 000000b
Powerg
ood
Self Refresh Latency Time (WM1)
Number of microseconds to access memory if memory is in Self
Refresh (0.5 us granularity).
00h = 0 us
01h = 0.5 us
02h = 1 us
...
3Fh = 31.5 us
NOTE: The value in this field corresponds to the memory latency
requested to the Display Engine when Memory is in Self Refresh.
The Display LP1 latency and watermark values (GTTMMADR offset
45118h) should be programmed to match the latency in this
register.
7:6 RWS 00b
Powerg
ood
Reserved for Future Use (RWSVD0)
5:0 RWS 000000b
Powerg
ood
Normal Latency Time (WM0)
Number of microseconds to access memory for normal memory
operations (0.1 us granularity).
00h = 0 us
01h = 0.1 us
02h = 0.2 us
...
3Fh = 6.3 us
B/D/F/Type: 0/0/0/MCHBAR PCU
Address Offset: 5D10–5D17h
Reset Value: 0000_0000_0000_0000h
Access: RWS
Size: 64 bits
Bit Attr
Reset
Value
RST/
PWR
Description