Datasheet

Datasheet, Volume 2 215
Processor Configuration Registers
2.16.2 MAD_DIMM_ch0—Address Decode Channel 0 Register
This register defines channel characteristics—number of DIMMs, number of ranks, size,
interleave options
.
B/D/F/Type: 0/0/0/MCHBAR_MCMAIN
Address Offset: 5004–5007h
Reset Value: 0060_0000h
Access: RW-L
Size: 32 bits
BIOS Optimal Default 00h
Bit Attr
Reset
Value
RST/
PWR
Description
31:26 RO 0h Reserved
25:24
RO 0h
Reserved
23 RO 0h Reserved
22 RW-L 1b Uncore
Enhanced Interleave mode (Enh_Interleave)
0 = Off
1 = On
21 RW-L 1b Uncore
Rank Interleave (RI)
0 = Off
1 = On
20 RW-L 0b Uncore
DIMM B DDR Width (DBW)
DIMM B width of DDR chips
0 = X8 chips
1 = X16 chips
19 RW-L 0b Uncore
DIMM A DDR Width (DAW)
DIMM A width of DDR chips
0 = X8 chips
1 = X16 chips
18 RW-L 0b Uncore
DIMM B number of Ranks (DBNOR)
0 = Single rank
1 = Dual rank
17 RW-L 0b Uncore
DIMM A number of Ranks (DANOR)
0 = Single rank
1 = Dual rank
16 RW-L 0b Uncore
DIMM A select (DAS)
Selects which of the DIMMs is DIMM A – should be the larger
DIMM:
0 = DIMM 0
1 = DIMM 1
15:8 RW-L 00h Uncore
Size of DIMM B (DIMM_B_Size)
Size of DIMM B in 256 MB multiples
7:0 RW-L 00h Uncore
Size of DIMM A (DIMM_A_Size)
Size of DIMM A in 256 MB multiples