Datasheet

Datasheet, Volume 2 211
Processor Configuration Registers
2.14.4 TC_SRFTP_C1—Self-Refresh Timing Parameters Register
This register provides Self-refresh timing parameters.
2.14.5 PM_PDWN_Config_C1—Power-down Configuration
Register
This register defines the power-down (CKE-off) operation – power-down mode, idle
timer, and global / per rank decision.
B/D/F/Type 0/0/0/MCHBAR MC1
Address Offset: 46A4–46A7h
Reset Value: 0000_B000h
Access: RW-L
Size: 32 bits
Bit Attr
Reset
Value
RST/
PWR
Description
31:16 RO 0 Reserved
15:12 RW-L Bh
Delay From SR Exit to First DDR Command
tXS = tRFC+10ns. Setup of tXS_offset is # of cycles for 10 ns.
Range is between 3 and 11 DCLK cycles
11:0 RO 0 Reserved
B/D/F/Type: 0/0/0/MCHBAR MC1
Address Offset: 44B0-44B3h
Default Value: 0000_0000h
Access: RW-L
Size: 32 bits
BIOS Optimal Default: 00000h
Bit Attr
Reset
Value
RST/
PWR
Description
31:13 RO 0h Reserved
12 RW-L 0b Uncore
Global power-down (GLPDN)
1 = Power-down decision is global for channel.
0 = A separate decision is taken for each rank.
11:8 RW-L 0h Uncore
Power-down mode (PDWN_mode)
Selects the mode of power-down. All encodings not in table are
reserved.
Note: When selecting DLL-off or APD-DLL off, DIMM MR0 register
bit 12 (PPD) must equal 0.
Note: When selecting APD, PPD or APD-PPD, DIMM MR0 register
bit 12 (PPD) must equal 1.
The value 0h (no power-down) is a don't care.
0h = No Power Down
1h = APD
2h = PPD
3h = APD - PPD
6h = DLL Off
7h = APD-DLL Off
7:0 RW-L 00h Uncore
Power-down idle timer (PDWN_idle_counter)
This defines the rank idle period in DCLK cycles that causes power-
down entrance.