Datasheet

Datasheet, Volume 2 209
Processor Configuration Registers
2.14 MCHBAR Registers in Memory Controller –
Channel 1
Table 2-16 lists the registers arranged by address offset. Register bit descriptions are in
the sections following the table.
2.14.1 TC_DBP_C1—Timing of DDR Bin Parameters Register
This register defines the BIN timing parameters for safe logic – tRCD, tRP, and tCL.
Table 2-16. MCHBAR Registers in Memory Controller – Channel 1 Register Address Map
Address
Offset
Register Symbol Register Name
Reset
Value
Access
0–43FFh RSVD Reserved — —
4400–4403h TC_DBP_C1 Timing of DDR Bin Parameters 0000_0666h RW-L
4404–4407h TC_RAP_C1 Timing of DDR Regular Access Parameters 0010_4044h RW-L
4428–442Bh SC_IO_LATENCY_C1 IO Latency configuration 0000_0000h RW-L
46A4–46A7h TC_SRFTP_C1 Self-Refresh Timing Parameters 0000_B000h RW-L
44B0-44B3h PM_PDWN_Config_C1 Power-down Configuration 0000_0000h RW-L
0–44C7h RSVD Reserved — —
44D0–4693h RSVD Reserved — —
4694–4697h TC_RFP_C1
Refresh Parameters
0000_980Fh
RW-L
4698–469Bh TC_RFTP_C1 Refresh Timing Parameters 46B4_1004h RW-L
469C–438Fh RSVD Reserved — —
B/D/F/Type 0/0/0/MCHBAR MC1
Address Offset: 4400–4403h
Reset Value: 0000_0666h
Access: RW-L
Size: 32 bits
Bit Attr
Reset
Value
RST/
PWR
Description
31:12 RO 0h Reserved
11:8 RW-L 6h
CAS Command Delay to Data Out of DDR Pins (tCL)
This field provides the delay from CAS command to data out of
DDR pins.
Range is 5 – 15.
Note:
1. This does not define the sample point in the I/O. This is
defined by training in round-trip register and other registers,
because this is also affected by board delays.
7:4 RW-L 6h
PRE to ACT Same Bank Delay (tRP)
Range is 4 – 15 DCLK cycles.
3:0 RW-L 6h
ACT to CAS (RD or WR) Same Bank Delay (tRCD)
Range is 4 – 15.