Datasheet

Processor Configuration Registers
206 Datasheet, Volume 2
2.13.2 TC_RAP_C0—Timing of DDR Regular Access Parameters
Register
This register provides the regular timing parameters in DCLK cycles.
2.13.3 SC_IO_LATENCY_C0—IO Latency Configuration Register
This register identifies the I/O latency per rank, and I/O compensation (global).
B/D/F/Type 0/0/0/MCHBAR MC0
Address Offset: 4004–4007h
Reset Value: 0010_4044h
Access: RW-L
Size: 32 bits
Bit Attr
Reset
Value
RST/
PWR
Description
31:24 RO 0h Reserved
23:16 RW-L 10h
Four-Activate Window
This field provides the time frame in which maximum of 4 ACT
commands to the same rank are allowed. The minimum value is
4*tRRD; the maximum value is 63 DCLK cycles.
15:12 RW-L 4h
Delay Internal WR to RD Transaction
This field provides the delay from internal WR transaction to
internal RD transaction. The minimum delay is 4 DCLK cycles,
whereas the maximum delay is 8 DCLK cycles.
11:8 RO 0h Reserved
7:4 RW-L 4h
Minimum Delay From CAS-RD to PRE
The minimum delay is 4 DCLK cycles; the maximum delay is 8
DCLK cycles.
3:0 RW-L 4h
Delay Between Two Act Commands
tRRD is the minimum delay between two ACT commands targeted
to different banks in the same rank. The minimum delay is 4 DCLK
cycles; the maximum delay is 7 cycles.
B/D/F/Type 0/0/0/MCHBAR MC0
Address Offset: 4028–402Bh
Reset Value: 0000_0000h
Access: RW-L
Size: 32 bits
Bit Attr
Reset
Value
RST/
PWR
Description
31:16 RO 0h Reserved
15:12 RW-L 0h IO latency Rank 1 DIMM 1
11:8 RW-L 0h IO latency Rank 0 DIMM 1
7:4 RW-L 0h IO latency Rank 1 DIMM 0
3:0 RW-L 0h IO latency Rank 0 DIMM 0