Datasheet

Processor Configuration Registers
204 Datasheet, Volume 2
2.12.23 LSTS2—Link Status 2 Register
2.12.24 AFE_BMUF0—AFE BMU Configuration Function 0 Register
2.12.25 AFE_BMUT0—AFE BMU Configuration Test 0 Register
B/D/F/Type: 0/0/0/DMIBAR
Address Offset: 9A–9Bh
Reset Value: 0000h
Access: RO-V
Size: 16 bits
BIOS Optimal Default 0000h
Bit Attr
Reset
Value
RST/
PWR
Description
15:1 RO 0h Reserved
0RO-V 0bUncore
Current De-emphasis Level (CURDELVL)
When the Link is operating at 5 GT/s speed, this reflects the level
of de-emphasis.
1 = -3.5 dB
0 = -6 dB
When the Link is operating at 2.5 GT/s speed, this bit is 0b.
B/D/F/Type: 0/0/0/DMIBAR
Address Offset: BC0–BC3h
Reset Value: E978873Ch
Access: RO, RW
Size: 32 bits
Bit Attr
Reset
Value
RST/
PWR
Description
31:14 RO
1 110100
101111
00 010b
Uncore
Reserved: Must be 1 110100 101111 00 010b when writing this
register.
13 RW 0b Uncore
PEG Half-Swing Enable (DETPNSEL)
This bit is for PEG half-swing de-emphasis enable.
0 = No De-emphasis at Half-Swing for 16 PEG lanes
1 = De-emphasis -3.5 db at Half-Swing 16 PEG lanes
12:0 RO
00111010
11100b
Uncore
Reserved: Must be 0011101011100b when writing this register.
B/D/F/Type: 0/0/0/DMIBAR
Address Offset: BCC–BCGh
Reset Value: 1000_000h
Access: RO, RW
Size: 32 bits
Bit Attr
Reset
Value
RST/
PWR
Description
31:25 RO 0h Uncore Reserved: Must be 0 when writing this register.
24 RO 1b Uncore Reserved: Must be 1 when writing this register.
23:5 RO 0h Uncore Reserved: Must be 0 when writing this register.
4RW 0bUncore
Transmit at Half Rail PEG (TXHALFRP)
This bit enables the transmitter to drive out a half rail to rail swing
on TXP/TXN when in PEG mode.
0 = Full swing for 16 PEG lanes
1 = Half swing for 16 PEG lanes
3:0 RO 0h Uncore Reserved: Must be 0 when writing this register.