Datasheet

Datasheet, Volume 2 173
Processor Configuration Registers
6 RW 0b Uncore
Common Clock Configuration (CCC)
0 = Indicates that this component and the component at the
opposite end of this Link are operating with asynchronous
reference clock.
1 = Indicates that this component and the component at the
opposite end of this Link are operating with a distributed
common reference clock.
The state of this bit affects the L0s Exit Latency reported in
LCAP[14:12] and the N_FTS value advertised during link training.
See L0SLAT at offset 22Ch.
5 RW-V 0b Uncore
Retrain Link (RL)
0 = Normal operation.
1 = Full Link retraining is initiated by directing the Physical Layer
TXTSSM from L0, L0s, or L1 states to the Recovery state.
This bit always returns 0 when read. This bit is cleared
automatically (no need to write a 0).
4 RW 0b Uncore
Link Disable (LD)
0 = Normal operation
1 = Link is disabled. Forces the TXTSSM to transition to the
Disabled state (using Recovery) from L0, L0s, or L1 states.
Link retraining happens automatically on 0 to 1 transition, just
like when coming out of reset.
Writes to this bit are immediately reflected in the value read from
the bit, regardless of actual Link state.
3 RO 0b Uncore
Read Completion Boundary (RCB)
Hardwired to 0 to indicate 64 byte.
2RO 0h Reserved
1:0 RW 00b Uncore
Active State PM (ASPM)
This field controls the level of ASPM (Active State Power
Management) supported on the given PCI Express Link.
00 = Disabled
01 = L0s Entry Supported
10 = Reserved
11 = L0s and L1 Entry Supported
B/D/F/Type: 0/6/0/PCI
Address Offset: B0–B1h
Reset Value: 0000h
Access: RO, RW, RW-V
Size: 16 bits
BIOS Optimal Default 00h
Bit Attr
Reset
Value
RST/
PWR
Description