Datasheet

Processor Configuration Registers
164 Datasheet, Volume 2
2.10.26 PM_CS6—Power Management Control/Status Register
B/D/F/Type: 0/6/0/PCI
Address Offset: 84–87h
Reset Value: 0000_0008h
Access: RO, RW
Size: 32 bits
BIOS Optimal Default 000000h
Bit Attr
Reset
Value
RST/
PWR
Description
31:16 RO 0h Reserved
15 RO 0b Uncore
PME Status (PMESTS)
This bit indicates that this device does not support PME#
generation from D3cold.
14:13 RO 00b Uncore
Data Scale (DSCALE)
This field indicates that this device does not support the power
management data register.
12:9 RO 0h Uncore
Data Select (DSEL)
This field indicates that this device does not support the power
management data register.
8RW 0bUncore
PME Enable (PMEE)
This bit indicates that this device does not generate PME# assertion
from any D-state.
0 = Disable. PME# generation not possible from any D State
1 = Enable. PME# generation enabled from any D State
The setting of this bit has no effect on hardware.
See PM_CAP[15:11]
7:4 RO 0h Reserved
3RO 1bUncore
No Soft Reset (NSR)
1 = Device is transitioning from D3hot to D0 because the power
state commands do not perform an internal reset.
Configuration context is preserved. Upon transition, no
additional operating system intervention is required to
preserve configuration context beyond writing the power state
bits.
0 = Devices do not perform an internal reset upon transitioning
from D3hot to D0 using software control of the power state
bits.
Regardless of this bit, the devices that transition from a D3hot to
D0 by a system or bus segment reset will return to the device state
D0 uninitialized with only PME context preserved if PME is
supported and enabled.
2RO 0h Reserved