Datasheet

Processor Configuration Registers
148 Datasheet, Volume 2
8RW1C 0b Uncore
Master Data Parity Error (PMDPE)
This bit is set by a Requester (Primary Side for Type 1
Configuration Space header Function) if the Parity Error Response
bit in the Command register is 1b and either of the following two
conditions occurs:
• Requester receives a Completion marked poisoned
• Requester poisons a write Request
If the Parity Error Response bit is 0b, this bit is never set.
This bit will be set only for completions of requests encountering
ECC error in DRAM.
Poisoned Peer-to-peer posted forwarded will not set this bit. They
are reported at the receiving port.
7RO 0bUncore
Fast Back-to-Back (FB2B)
Not Applicable or Implemented. Hardwired to 0.
6RO 0h Reserved
5RO 0bUncore
66/60 MHz capability (CAP66)
Not Applicable or Implemented. Hardwired to 0.
4RO 1bUncore
Capabilities List (CAPL)
Indicates that a capabilities list is present. Hardwired to 1.
3RO-V 0bUncore
INTx Status (INTAS)
Indicates that an interrupt message is pending internally to the
device. Only PME and Hot Plug sources feed into this status bit (not
PCI INTA-INTD assert and deassert messages). The INTA Assertion
Disable bit, PCICMD1[10], has no effect on this bit.
Note that INTA emulation interrupts received across the link are
not reflected in this bit.
2:0 RO 0h Reserved
B/D/F/Type: 0/6/0/PCI
Address Offset: 6–7h
Reset Value: 0010h
Access: RW1C, RO, RO-V
Size: 16 bits
BIOS Optimal Default 0h
Bit Attr
Reset
Value
RST/
PWR
Description