Datasheet

Datasheet, Volume 2 143
Processor Configuration Registers
2.10 PCI Device 6 Configuration Registers
Table 2-12 lists the registers arranged by address offset. Register bit descriptions are in
the sections following the table.
Table 2-12. PCI Device 6 Register Address Map (Sheet 1 of 2)
Address
Offset
Register
Symbol
Register Name Reset Value Access
0–1h VID6 Vendor Identification 8086h RO
2–3h DID6 Device Identification 010Dh RO-FW
4–5h PCICMD6 PCI Command 0000h RW, RO
6–7h PCISTS6
PCI Status
0010h
RW1C, RO,
RO-V
8h RID6 Revision Identification 00h RO-FW
9–Bh CC6 Class Code 06_0400h RO
Ch CL6 Cache Line Size 00h RW
Dh RSVD Reserved 0h RO
Eh HDR6 Header Type 01h RO
F–17h RSVD Reserved 0h RO
18h PBUSN6 Primary Bus Number 00h RO
19h SBUSN6 Secondary Bus Number 00h RW
1Ah SUBUSN6 Subordinate Bus Number 00h RW
1Bh RSVD Reserved 0h RO
1Ch IOBASE6 I/O Base Address F0h RW
1Dh IOLIMIT6 I/O Limit Address 00h RW
1E–1Fh SSTS6 Secondary Status 0000h RW1C, RO
20–21h MBASE6 Memory Base Address FFF0h RW
22–23h MLIMIT6 Memory Limit Address 0000h RW
24–25h PMBASE6 Prefetchable Memory Base Address FFF1h RW, RO
26–27h PMLIMIT6 Prefetchable Memory Limit Address 0001h RW, RO
28–2Bh PMBASEU6 Prefetchable Memory Base Address Upper 0000_0000h RW
2C–2Fh PMLIMITU6 Prefetchable Memory Limit Address Upper 0000_0000h RW
30–33h RSVD Reserved 0h RO
34h CAPPTR6 Capabilities Pointer 88h RO
35–3Bh RSVD Reserved 0h RO
3Ch INTRLINE6 Interrupt Line 00h RW
3Dh INTRPIN6 Interrupt Pin 01h RW-O, RO
3E–3Fh BCTRL6 Bridge Control 0000h RO, RW
40–7Fh RSVD Reserved 0h RO
80–83h PM_CAPID6 Power Management Capabilities C803_9001h RO, RO-V
84–87h PM_CS6 Power Management Control/Status 0000_0008h RO, RW
88–8Bh SS_CAPID Subsystem ID and Vendor ID Capabilities 0000_800Dh RO
8C–8Fh SS Subsystem ID and Subsystem Vendor ID 0000_8086h RW-O
90–91h MSI_CAPID Message Signaled Interrupts Capability ID A005h RO