Datasheet

Processor Configuration Registers
130 Datasheet, Volume 2
2.8 PCI Device 2 Configuration Registers
Table 2-10 lists the registers arranged by address offset. Register bit descriptions are in
the sections following the table.
Table 2-10. PCI Device 2 Configuration Register Address Map
Address
Offset
Register
Symbol
Register Name
Reset
Value
Access
0–1h VID2 Vendor Identification 8086h RO
2–3h DID2 Device Identification 0102h RO-V, RO-FW
4–5h PCICMD2 PCI Command 0000h RW, RO
6–7h PCISTS2 PCI Status 0090h RO, RO-V
8h RID2 Revision Identification 00h RO-FW
9–Bh CC Class Code 03_0000h RO-V, RO
Ch CLS Cache Line Size 00h RO
Dh MTXT2 Master Latency Timer 00h RO
Eh HDR2 Header Type 00h RO
Fh RSVD Reserved 0h RO
10–17h GTTMMADR
Graphics Translation Table, Memory Mapped
Range Address
0000_0000_
0000_0004h
RW, RO
18–1Fh GMADR
Graphics Memory Range Address 0000_0000_
0000_000Ch
RO, RW-L,
RW
20–23h IOBAR I/O Base Address 0000_0001h RW, RO
24–2Bh RSVD Reserved 0h RO
2C–2Dh SVID2 Subsystem Vendor Identification 0000h RW-O
2E–2Fh SID2 Subsystem Identification 0000h RW-O
30–33h ROMADR Video BIOS ROM Base Address 0000_0000h RO
34h RSVD Reserved 90h RO-V
35–3Bh RSVD Reserved 0h RO
3Ch RSVD Reserved 00h RW
3Dh INTRPIN Interrupt Pin 01h RO
3Eh MINGNT Minimum Grant 00h RO
3Fh MAXLAT Maximum Latency 00h RO
40–61h RSVD Reserved — —
62–62h MSAC Multi Size Aperture Control 02h RW, RW-K
63–FFh RSVD Reserved — —