Datasheet
Processor Configuration Registers
122 Datasheet, Volume 2
2.6.43 RCTL—Root Control Register
This register allows control of PCI Express Root Complex specific parameters. The
system error control bits in this register determine if corresponding SERRs are
generated when our device detects an error (reported in this device's Device Status
register) or when an error message is received across the link. Reporting of SERR as
controlled by these bits takes precedence over the SERR Enable in the PCI Command
Register.
B/D/F/Type: 0/1/0–2/PCI
Address Offset: BC–BDh
Reset Value: 0000h
Access: RO, RW
Size: 16 bits
BIOS Optimal Default 000h
Bit Attr
Reset
Value
RST/
PWR
Description
15:4 RO 0h Reserved
3RW 0bUncore
PME Interrupt Enable (PMEIE)
0 = Disable. No interrupts are generated as a result of receiving
PME messages.
1 = Enable interrupt generation upon receipt of a PME message as
reflected in the PME Status bit of the Root Status Register. A
PME interrupt is also generated if the PME Status bit of the
Root Status Register is set when this bit is set from a cleared
state.
If the bit changes from 1 to 0 and an interrupt is pending, the
interrupt is de-asserted.
2RW 0bUncore
System Error on Fatal Error Enable (SEFEE)
Controls the Root Complex's response to fatal errors.
0 = Disable. No SERR generated on receipt of fatal error.
1 = Enable. SERR should be generated if a fatal error is reported
by any of the devices in the hierarchy associated with this
Root Port, or by the Root Port itself.
1RW 0bUncore
System Error on Non-Fatal Uncorrectable Error Enable
(SENFUEE)
Controls the Root Complex's response to non-fatal errors.
0 = Disable. No SERR generated on receipt of non-fatal error.
1 = Enable. SERR should be generated if a non-fatal error is
reported by any of the devices in the hierarchy associated
with this Root Port, or by the Root Port itself.
0RW 0bUncore
System Error on Correctable Error Enable (SECEE)
Controls the Root Complex's response to correctable errors.
0 = Disable. No SERR generated on receipt of correctable error.
1 = Enable. SERR should be generated if a correctable error is
reported by any of the devices in the hierarchy associated
with this Root Port, or by the Root Port itself.