Specification Update

R
Intel
®
E7205 Chipset MCH
Specification Update 9
Errata
1. tVAL(min) Timing Is Not Meeting AGP 3.0 Specification
Problem: During simulation studies, it was determined that the AGP signals were not meeting the tVAL(min) of
1ns.
Implication: AGP interface is susceptible to latching invalid data.
Workaround: Minimum trace lengths for the AGP common clock and source synchronous signals have increased to
offset this timing violation. Refer to latest platform design guide.
Status: No fix planned for this erratum. Issue resolved by board workaround.
2. AGP Prefetch Cache Must Be Disabled
Problem: System hangs can occur during AGP transactions when the AGP Prefetcher is enabled.
Implication: System hang.
Workaround: Disable AGP Prefetch Cache by clearing bit 0 of AGP Miscellaneous Register (Device 1 Function 0
Offset A0-A3h).
Status: No fix planned for this erratum. System performance is not affected by this erratum.