Datasheet

Register Description
R
54 Intel
®
82845 MCH for DDR Datasheet
3.5.16 DRA—DRAM Row Attribute Registers (Device 0)
Offset: 70–73h (DRA0–DRA3)
Default: 00h
Access: R/W
Size: 8 bits
The DRAM Row Attribute Register defines the page sizes to be used when accessing different
pairs of rows. Each nibble of information in the DRA registers describes the page size of a pair of
rows:
Row 0, 1 = 70h
Row 2, 3 = 71h
Row 4, 5 = 72h (Not used; see note)
Row 6, 7 = 73h (Not used; see note)
Note: Must contain default value of 00h
7 6 4 3 2 0
Reserved Row attribute for Row 1 Reserved Row Attribute for Row 0
7 6 4 3 2 0
Reserved Row attribute for Row 3 Reserved Row Attribute for Row 2
7 6 4 3 2 0
Reserved Row attribute for Row 5 Reserved Row Attribute for Row 4
7 6 4 3 2 0
Reserved Row attribute for Row 7 Reserved Row Attribute for Row 6
Bit Description
7 Reserved.
6:4 Row Attribute for Odd-Numbered Row (RAODD). This 3-bit field defines the page size of the
corresponding row.
001 = 2 KB
010 = 4 KB
011 = 8 KB
100 = 16 KB
Others = Reserved
3 Reserved.
2:0 Row Attribute for Even-Numbered Row (RAEVEN). This 3-bit field defines the page size of
the corresponding row.
001 = 2 KB
010 = 4 KB
011 = 8 KB
100 = 16 KB
Others = Reserved