Datasheet

Intel

82845 MCH for DDR Datasheet 53

3.5.15 DRB[0:7]—DRAM Row Boundary Registers (Device 0)

Offset: 60–67h (DRB0–DRB7)

Default: 00h

Access: R/W

Size: 8 bits

The DRAM Row Boundary Register defines the upper boundary address of each pair of DRAM

rows with a granularity of 32 MB. Each row has its own single-byte DRB register. For example, a

value of 1 in DRB0 indicates that 32 MB of DRAM has been populated in the first row.

Row 0 = 60h

Row 1 = 61h

Row 2 = 62h

Row 3 = 63h

Row 4 = 64h (Note 1)

Row 5 = 65h (Note 1)

Row 6 = 66h (Note 1)

Row 7 = 67h (Note 1)

DRB0 = Total memory in row 0 (in 32 MB increments)

DRB1 = Total memory in row 0 + row 1 (in 32 MB increments)

----

DRB3 = Total memory in row 0 + row 1 + row 2 + row 3 (in 32 MB increments)

Notes:

1. DRB[4:7] must be programmed with value contained in DRB3.

Each row is represented by a byte. Each byte has the following format.

Bit Description

7:0 DRAM Row Boundary Address. This 8-bit value defines the upper and lower addresses for

each DRAM row. This 8-bit value is compared against a set of address lines to determine the

upper address limit of a particular row.