Datasheet

Signal Description
R
Intel
®
82845 MCH for DDR Datasheet 23
2.2 DDR SDRAM Interface Signals
Signal Name Type Description
SCS[3:0]# O
CMOS
Chip Select: These signals select the particular SDRAM components
during the active state.
Note: There is one SCS# signal per SDRAM row. This signal can be
toggled on every rising SCKx clock edge.
SMA[12:0] O
CMOS
Multiplexed Memory Address: These signals are used to provide the
multiplexed row and column address to SDRAM.
SBS[1:0] O
CMOS
Memory Bank Select: SBS[1:0] define the banks that are selected within
each SDRAM row. The SMA and SBS signals combine to address every
possible location in a SDRAM device.
SRAS# O
CMOS
SDRAM Row Address Strobe: SRAS# is Used with SCAS# and SWE#
(along with SCS#) to define the DRAM commands.
SCAS# O
CMOS
SDRAM Column Address Strobe: SCAS# is used with SRAS# and
SWE# (along with SCS#) to define the SDRAM commands.
SWE# O
CMOS
Write Enable: SWE# is used with SCAS# and SRAS# (along with SCS#)
to define the SDRAM commands.
SDQ[63:0] I/O
CMOS
Data Lines: These signals are used to interface to the SDRAM data bus.
SCB[7:0] I/O
CMOS
Check Bit Data Lines: These signals are used to interface to the
SDRAM ECC signals.
SDQS[8:0] I/O
CMOS
Data Strobes: The following list indicates the data byte and strobe
signal association:
Signal Data Byte
SDQS8 SCB[7:0]
SDQS7 SDQ[63:56]
SDQS6 SDQ[55:48]
SDQS5 SDQ[47:40]
SDQS4 SDQ[39:32]
SDQS3 SDQ[31:24]
SDQS2 SDQ[23:16]
SDQS1 SDQ[15:8]
SDQS0 SDQ[7:0]
SCKE[3:0] O
CMOS
Clock Enable: These pins are used to signal a self-refresh or
Powerdown command to a SDRAM array when entering system
suspend. There is one SCKE per SDRAM row. These signals can be
toggled on every rising SCKx edge.
RCVENOUT# O
CMOS
Clock Output: RCVENOUT# is Part of the feedback used to enable the
DQS input buffers during reads. This signal Connects to RCVENIN#.
RCVENIN# I
CMOS
Clock Input: RCVENIN# connects to RCVENOUT#. This input (driven
from RCVENOUT#) enables the DQS input buffers during reads.