Datasheet

Electrical Characteristics
R
Intel
®
82845 MCH for DDR Datasheet 121
Table 20. Signal Groups
Signal
Group
Signal Type
Signals
Host Interface Signal Groups
(a) AGTL+ I/O ADS#, BNR#, BR0#,DBSY#, DBI[3:0]#, DRDY#,
HA[31:3]#, HADSTB[1:0] #, HD[63:0]#,HDSTBP[3:0]#,
HDSTBN[3:0]#, HIT#, HITM#, HREQ[4:0]#
(b) AGTL+ Common Clock
Output
BPRI#, CPURST#, DEFER#, HTRDY#, RS[2:0]#
(c) AGTL+ Common Clock Input HLOCK#
(d) Host Reference Voltages HVREF, HSWING[1:0]
AGP Interface Signal Groups
(e) AGP I/O AD_STB0, AD_STB0#, AD_STB1, AD_STB1#,
G_FRAME#, G_IRDY#, G_TRDY#, G_STOP#,
G_DEVSEL#, G_AD[31:0], G_CBE[3:0]#, G_PAR
(f) AGP Input PIPE#, SBA[7:0], RBF#, WBF#, SB_STB, SB_STB#,
G_REQ#
(g) AGP Output ST[2:0], G_GNT#
(h) AGP Reference Voltage AGPREF
Hub Interface Signal Groups
(i) Hub Interface’s CMOS I/O HI_[10:0], HI_STB, HI_STB#
(j) Hub Interface Reference
Voltage
HI_REF
DDR Interface Signal Groups
(k) DDR CMOS I/O SDQ[63:0], SCB[7:0], SDQS[8:0]
(l) DDR CMOS Output SCS[3:0]#, SMA[12:0], SBS[1:0], SRAS#, SCAS#, SWE#,
SCKE[3:0], RCVENOUT#, SCK[5:0], SCK[5:0]#
(m) DDR CMOS Input RCVENIN#
(n) DDR Reference Voltage SDREF
Clocks, Reset, and Miscellaneous Signal Groups
(o) CMOS Input TESTIN#
(p) CMOS Input RSTIN# (3.3V)
(q) CMOS Clock Input BCLK, BCLK#
(v) CMOS Clock Input 66IN
I/O Buffer Supply Voltages
(r) AGTL+ Termination Voltage VTT
(s) 1.5 V Core and AGP Voltage VCC1_5
(t) 1.8 V Hub Interface Voltage VCC1_8
(u) 2.5 V DDR Supply Voltage VCCSM