Datasheet

Functional Description
R
Intel
®
82845 MCH for DDR Datasheet 111
5.2.3 Memory Address Translation and Decoding
The 845 MCH contains address decoders that translate the address received on the system bus or
the hub interface. Decoding and translation of these addresses vary with the four SDRAM types.
Also, the number of pages, page sizes, and densities supported vary with the type. In general, the
MCH supports 64-Mb, 128-Mb, 256-Mb, and 512-Mb SDRAM devices. The multiplexed
row/column address
to the SDRAM memory array is provided by the SBS[1:0] and SMA[12:0]
signals. These addresses are derived from the system address bus as defined by Table 14 for
SDRAM devices.
Table 14. Address Translation and Decoding
Tech Configuration Row size
Page size
Row / Column
/ Bank
Addr BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
64Mb 1Meg x 16 x 4bks 32 MB 12x8x2 Row 24 11 12 24 13 14 15 16 23 22 21 20 19 18 17
2 KB Col AP 10 9 8 7 6 5 4 3
64Mb 2Meg x 8 x 4bks 64 MB 12x9x2 Row 25 13 12 24 25 14 15 16 23 22 21 20 19 18 17
4 KB Col AP 11 10 9 8 7 6 5 4 3
128Mb 2Meg x 16 x 4bks 64 MB 12x9x2 Row 25 13 12 24 25 14 15 16 23 22 21 20 19 18 17
4 KB Col AP 11 10 9 8 7 6 5 4 3
128Mb 4Meg x 8 x 4bks 128 MB 12x10x2 Row 26 14 13 26 25 24 15 16 23 22 21 20 19 18 17
8 KB Col AP 12 11 10 9 8 7 6 5 4 3
256Mb 4Meg x 16 x 4bks 128 MB 13x9x2 Row 26 13 12 26 24 25 14 15 16 23 22 21 20 19 18 17
4 KB Col AP 11 10 9 8 7 6 5 4 3
256Mb 8Meg x 8 x 4bks 256 MB 13x10x2 Row 27 14 13 27 26 25 24 15 16 23 22 21 20 19 18 17
8 KB Col AP 12 11 10 9 8 7 6 5 4 3
512Mb 8Meg x 16 x 4bks 256 MB 13x10x2 Row 27 14 13 27 26 25 24 15 16 23 22 21 20 19 18 17
8 KB Col AP 12 11 10 9 8 7 6 5 4 3
512Mb 16Meg x 8 x 4bks 512 MB 13x11x2 Row 28 14 15 27 26 25 24 28 16 23 22 21 20 19 18 17
16 KB Col 13 AP 12 11 10 9 8 7 6 5 4 3