Datasheet

Functional Description
R
Intel
®
82845 MCH for DDR Datasheet 109
5.2 System Memory Interface
The 845 chipset can be configured to support DDR200/266 memory.
5.2.1 Double Data Rate (DDR) SDRAM Interface Overview
The MCH integrates a system memory SDRAM controller with a 64-bit wide interface and twelve
system memory clock signals.
The MCH includes support for:
• Up to 2 GB of 200/266 MHz DDR SDRAM
• DDR200/266 unbuffered 184 pin DDR SDRAM DIMMs
• Maximum of 2 DIMMs, single-sided and/or double-sided
•
Configurable optional ECC
The two bank-select lines SBS[1:0] and the thirteen address lines (SMA[12:0]) allow the MCH to
support 64-bit wide DIMMs using 64-Mb, 128-Mb, 256-Mb, and 512-Mb SDRAM technologies.
While address lines SMA[9:0] determine the starting address for a burst, burst lengths are fixed at
four. Four chip selects SCS# lines allow a maximum of two rows with single-sided SDRAM
DIMMs and four rows with double-sided SDRAM DIMMs.
The MCH’s system memory controller targets CAS latencies of 2 and 2.5 clocks for SDRAM. The
MCH provides refresh functionality with a programmable rate (normal SDRAM rate is
1 refresh/15.6 µs).
5.2.2 Memory Organization and Configuration
In the following discussion the term row refers to a set of memory devices that are simultaneously
selected by a SCS# signal. The MCH supports a maximum of four rows of memory. For the
purposes of this discussion, a “side” of a DIMM is equivalent to a “row” of SDRAM devices.
Table 12. Supported DIMM Configurations
Density 64 Mbit 128 Mbit 256 Mbit 512 Mbit
Device
Width
X8 X16 X8 X16 X8 X16 X8 X16
Single \
Double
SS/DS SS/DS SS/DS SS/DS SS/DS SS/DS SS/DS SS/DS
184 pin
DDR
DIMMs
64 MB /
128 MB
32 MB /
NA
128 MB /
256 MB
64 MB /
NA
256 MB /
512 MB
128 MB /
NA
512 MB /
1024 MB
256 MB /
NA
NOTE: Double-sided X16 DDR SDRAM devices are not supported.