Errata
10 Intel® 3200/3210 Chipset Memory Controller Hub (MCH) Specification Update
5Errata
1. PCIe 1.1 cards in PCIe slots off the MCH lead to boot failures.
Problem: The Intel® X38 Express Chipset sets the TS1 Ordered Set - Symbol 4 Bit[6] to 1b when
a PCIe 1.1 card is plugged in. This is a reserved bit which is used in PCIe 2.0 to
broadcast support for selectable de-emphasis. PCIe 1.1 Specification states that Bit[6]
should be set to 0b. With some 2.5 GT/s PCIe 1.1 I/O cards of widths x8/x4/x1, system
restarts and hangs were exhibited during PCIe link initialization when populated in MCH
slots.
Implication: System unable to train some 2.5 GT/s PCIe 1.1 cards that don't comply with the PCIe
1.1 Specification. Failures have occurred across multiple vendors and different types of
PCIe 1.1 cards.
Workaround: Contact your Intel field representative for the latest BIOS information. Modification to
the Link Stability/Recovery Algorithm will fix this issue when using non-compliant cards
but customers should continue working with their card vendors for PCIe 1.1 Spec
compliancy.
Status: No Fix. For affected steppings, see the Summary Table of Changes.
2. IERR due to DMI/PCIe Link Not Trained
Problem: The MCH has a rare meta-stability condition within the DMI/PCIe [3210: DMI/primary
PCIe and secondary PCIe] receiver PLL divider circuitry. The MCH DMI/PCIe [3210:
DMI/primary PCIe] receiver may not be locked at the correct internal clock phase
during warm or cold reset - causing the DMI [3210: DMI/primary PCIe] link to not
train. [3210: The MCH secondary PCIe receiver may not be locked - causing the
secondary PCIe link to not train. Each lock independently.] If the DMI/PCIe receiver
divider locked to the correct clock phase, the receiver divider stays locked - and the
DMI/PCIe [3210: DMI/primary PCIe and secondary PCIe] link stays trained - until the
next warm or cold reset.
Implication:
• If the rare meta-stability condition occurs, the processor may assert IERR due to
traffic across the DMI link not completing. If the ICH Watch Dog Timer is enabled,
the timer will time out and reboot the system. On the subsequent reset, the DMI/
PCIe [3210: DMI/primary PCIe] receiver may lock at the correct phase - and
normal operation continues.
• In the extremely rare event that meta-stability occurs on back-to-back resets, the
system could hang due to the DMI link not being trained. The Watch Dog Timer has
timed out once, and would not timeout again to reboot the system. Intel has not
observed the occurrence of back-to-back meta-stable conditions.
• [3210:If the rare meta-stability condition occurs on the secondary PCIe receiver
PLL divider circuitry, a PCIe add-in card present in the slot would not be trained.]
Workaround:
• BIOS enable ICH Watch Dog Timer. If an external BMC is present, the BMC should
ignore IERR during reset and POST. See latest Intel
® X38 Express Chipset Family
and 3200/3210 Chipset Family BIOS Specification for proper handling of ignoring
IERR.
• [3210: If a PCIe add-in card is present but not trained, BIOS resets the secondary
PCIe link to retrain the card. See latest BIOS specification.]
Status: No Fix.