Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide April 2004 Order Number: 278944-001
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Contents Contents 1 About This Document ......................................................................................................................7 1.1 2 Introduction ...................................................................................................................................... 9 2.1 2.2 2.3 2.4 3 Terminology and Definitions ................................................................................................. 7 Product Overview ..........................
Contents 7.2.4.2 8 PICMG 1.2 System Overview ................................................................ 52 Power Considerations ................................................................................................................... 57 8.1 8.2 Analog Power Pins ............................................................................................................. 57 Power Sequencing....................................................................................................
Contents 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Secondary Bus Frequency Initialization...................................................................................... 33 PCI-X Initialization Pattern.......................................................................................................... 34 Intel® 31154 133 MHz PCI Bridge Decoupling Recommendations ............................................ 38 Add-in Card Routing Parameters..............................
Contents Revision History 6 Date Revision April 2004 001 Description Initial release Intel® 31154 133 MHz PCI Bridge Design Guide
About This Document 1 About This Document This document provides layout information and guidelines for designing platform or add-in board applications with the Intel® 31154 133 MHz PCI Bridge. This document is intended to be used as a guideline only. Intel recommends that you employ bestknown design practices with board-level simulation, signal-integrity testing, and validation for a robust design.
About This Document Table 1. Terminology and Definition (Sheet 2 of 2) Term Definition An aggressor network is a network that transmits a coupled signal to another network. Zo Aggressor Zo Victim Network Zo Zo Aggressor Network B3337-01 Victim A network that receives a coupled cross-talk signal from another network is a called the victim network. Network A network is the trace of a PCB that completes an electrical connection between two or more components.
Introduction 2 Introduction 2.1 Product Overview The Intel® 31154 133 MHz PCI Bridge (called hereafter the “31154”) is a PCI component that functions as a highly concurrent, low-latency transparent bridge between two PCI buses. The 31154 can operate as a PCI-to-PCI bridge in the configurations shown in Table 2. Table 2. PCI-to-PCI Bridge Configurations Primary Bus Interface Secondary Bus Interface PCI 2.3 PCI 2.3 PCI 2.3 PCI-X PCI-X PCI 2.
Introduction The 31154 has additional hardware support for CompactPCI* Hot Swap and Redundant System Slot via queue flush, arbiter lock, and clock output tristating. The 31154 supports any combination of 32-bit and 64-bit data transfers on its primary and secondary bus interfaces. The 31154 is 33/66 MHz capable in conventional PCI mode, and can run at 66 MHz, 100 MHz, or 133 MHz when operating in PCI-X mode, depending upon its surrounding environment. 2.2 Features List Table 3.
Introduction 2.3 Related External Specifications • • • • • • 2.4 PCI Local Bus Specification, Revision 2.3 PCI-to-PCI Bridge Architecture Specification, Revision 1.1 PCI Bus Power Management Interface Specification, Revision 1.1 Compact PCI Hot Swap Specification, Revision 2.1 R2.0 PCI-X Addendum to the PCI Local Bus Specification, Revision 1.1 Embedded PCI-X Specification PICMG 1.2 R1.0 References This section lists references that can be useful with a 31154 application.
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Package Information Package Information 3 The Intel® 31154 133 MHz PCI Bridge is offered in a 421-lead PBGA package. The mechanical dimensions for this package are provided in Figure 2 on page 14. Figure 3 on page 15 and Figure 4 on page 16 show the 421-lead PBGA, mapped by pin function. These figures are helpful in placing components around the 31154 for the layout of a PCB. To simplify routing and minimize the number of cross traces, keep this layout in mind when placing components on your board.
Package Information Figure 2. Intel® 31154 133 MHz PCI Bridge Package Notes: 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2 3 Dimension is measured at the maximum solder ball diameter, parallel to primary datum Ø 2 Primary datum and seating plane are defined by the spherical crowns of the solder balls. Ø 0.30 S C A S 0.90 0.60 22 23 20 21 18 19 17 16 14 12 10 8 6 15 13 11 9 7 5 B S 1.27 0.127 A 31.00 ± 0.10 26.00 ± 0.
Package Information Figure 3.
Package Information Figure 4.
Package Information 3.1 Total Signal Count Table 4.
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Terminations 4 Terminations This chapter details all the recommended Intel® 31154 133 MHz PCI Bridge terminations required for the different operating modes. The chapter provides the recommended pull-up and pull-down terminations for a 31154 layout. Table 5 lists these 31154 termination values. Note that for motherboards, the PCI Local Bus Specification, Revision 2.3 requires that the PCI signals provide the termination resistors. Table 5.
Terminations Table 5. Pull-Up/Pull-Down Terminations (Sheet 2 of 9) Signal Pull-Up/Pull-Down or Termination (See Note 1) P_GNT# Connect to GNT# of the primary PCI bus. P_IDSEL# Connect to one of the AD lines of the primary PCI bus or to the IDSEL# signal of the PCI edge connector (for add-in card applications). P_M66EN Connect to the M66EN signal of the primary PCI bus of the PCI add-in card finger. P_PAR Connect to PAR of the primary PCI bus. P_PAR64 Connect to PERR# of the primary PCI bus.
Terminations Table 5. Signal S_AD[31:17] Pull-Up/Pull-Down Terminations (Sheet 3 of 9) Pull-Up/Pull-Down or Termination (See Note 1) Comments These signals can be used as IDSEL lines and are connected to IDSEL of the secondary PCI bus through an external series coupling resistor (a resistor of 2 KΩ is used on the customer reference board). PCI Clocks P_CLK Connect to the PCI clock on the primary PCI bus. S_BRGCLKO When the internal clock of the 31154 is used, connect to S_CLKI through a 33.
Terminations Table 5. Signal Pull-Up/Pull-Down Terminations (Sheet 4 of 9) Pull-Up/Pull-Down or Termination (See Note 1) Comments When the internal clock of the 31154 is used, pull high to VCC33 through an external 8.2 KΩ resistor. S_GCLKOEN When an external clock source is used, tie to GND through a 330 Ω external resistor. All secondary clock outputs (S_CLKO[8:0] and S_BRGCLKO) asynchronously tristate. When an external clock source is used, tie S_CLKOEN[3:0] to a stable value.
Terminations Table 5. Pull-Up/Pull-Down Terminations (Sheet 5 of 9) Signal Pull-Up/Pull-Down or Termination (See Note 1) Comments For Hot Swap: • Depending on Primary PCI Bus frequency HS_FREQ[1:0] 00 = PCI Mode, 33 or 66 MHz (default) Only valid when HS_SM = 1. 01 = PCI-X 66 MHz 0 = Tie low to GND. 1 = Pull high to 3.3 V through external 8.2 KΩ resistor. 10 = PCI-X 100 MHz 11 = PCI-X 133 MHz When not using Hot Swap: • Tie low to GND.
Terminations Table 5. Signal Pull-Up/Pull-Down Terminations (Sheet 6 of 9) Pull-Up/Pull-Down or Termination (See Note 1) Comments To enable Opaque Memory Base/Limit Registers to establish a private memory space for secondary bus usage: OPAQUE_EN • Pull high to 3.3 V through an external 8.2 KΩ resistor. To disable Opaque Memory Base/Limit Registers: • Pull low to GND through an external 220 Ω resistor (default).
Terminations Table 5. Signal Pull-Up/Pull-Down Terminations (Sheet 7 of 9) Pull-Up/Pull-Down or Termination (See Note 1) Comments JTAG TCK Pull low when not used. TDI When not used, pull up to 3.3 V through an external 8.2 KΩ resistor. TDO NC when not used TRST# When not used, pull low to GND through an external 1 KΩ resistor. TMS When not used, pull up to 3.3 V through an external 8.2 KΩ resistor. SCAN_EN For normal operation, tie low to GND. For normal operation, tie to 0000 or 0111.
Terminations Table 5. Pull-Up/Pull-Down Terminations (Sheet 8 of 9) Signal Pull-Up/Pull-Down or Termination (See Note 1) RSTV0 Tie to GND through a 0 Ω external resistor. RSRV1/CRSTEN Tie to GND through a 0 Ω external resistor. Comments S_M66EN is meaningful only when S_PCIXCAP is connected to GND (that is, when the secondary PCI bus is in legacy PCI mode). For designs without secondary PCI slot: • When the secondary PCI devices (and loading) support 66 MHz PCI bus, pull up to 3.3 V through an 8.
Terminations Table 5. Signal Pull-Up/Pull-Down Terminations (Sheet 9 of 9) Pull-Up/Pull-Down or Termination (See Note 1) • When forced retirement of the 31154 internal request queues and data buffer is not desired in the application, this pin must be pulled up to 3.3 V through an 8.2 KΩ resistor. Comments • As soon as NT_MASK# is asserted, it must not be de-asserted until the QE pin is asserted.
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PCI/PCI-X Interface 5 PCI/PCI-X Interface This chapter provides guidelines for designing with the Intel® 31154 133 MHz PCI Bridge PCI/PCI-X bus interface in your application. 5.1 PCI/PCI-X Voltage Levels The Intel® 31154 133 MHz PCI Bridge supports the 5 V PCI signaling interface as well as 3.3 V. Table 6 is provided as a reference for the PCI/PCI-X signaling levels. A complete PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a can be found on the www.pcisig.com website. Table 6.
PCI/PCI-X Interface 5.3 IDSEL Lines The IDSEL lines act as chip selects during the configuration cycles. Configuration cycles allow read and write access to one of the device configuration space registers. As in PCI, the IDSEL lines can be mapped to upper address lines, which are unused during the configuration cycles. 5.3.1 Primary IDSEL Line Figure 5 provides an example of the 31154 used as an embedded controller connected to four PCI devices.
PCI/PCI-X Interface 5.3.3 Secondary IDSEL Masking The 31154 supports private devices through the use of IDSEL masking. When the IDSEL_MASK pin is sampled as 1b on the trailing edge of P_RST#, the default value for the Secondary IDSEL Select Register (SISR) is 001Fh to mask devices 0–4 (refer to the Intel® 31154 133 MHz PCI Bridge Developer’s Manual for more information). 5.3.4 Secondary Clock Control The 31154 can disable its secondary clock outputs individually or globally.
PCI/PCI-X Interface 5.6 PCI-X Initialization Clocking Modes Both of the PCI bus interfaces can operate at a variety of frequencies, and in either conventional PCI mode, or in PCI-X mode. Each interface establishes the bus mode and frequency when coming out of its corresponding bus segment reset sequence. The resultant mode and frequency is dependent upon the device capabilities reported, in addition to any system-specific loading information. 5.6.
PCI/PCI-X Interface Table 8. Table 9.
PCI/PCI-X Interface Table 10 describes the bus mode and frequency initialization pattern that the 31154 signals on its secondary bus when coming out of S_RST#, after having evaluated the above information. Table 10. PCI-X Initialization Pattern DEVSEL# STOP# TRDY# Clock Period (Ns) Mode Max. Deasserted Deasserted PCI 33 62.5 PCI 66 30 Clock Frequency (MHz) Min. 1 Min. 1 Max. 30 62.
Routing Guidelines Routing Guidelines 6 This chapter provides some basic routing guidelines for layout and design of a printed circuit board (PCB) using the Intel® 31154 133 MHz PCI Bridge. The high-speed clocking required when designing with the 31154 requires special attention to signal integrity. In fact, it is highly recommended that the board design be simulated to determine optimum layout for signal integrity.
Routing Guidelines 6.1 Crosstalk Crosstalk is caused by capacitive and inductive coupling between signals. Crosstalk is composed of both backward and forward crosstalk components. Backward crosstalk creates an induced signal on a victim network that propagates in the opposite direction of the aggressor signal. Forward crosstalk creates a signal that propagates in the same direction as the aggressor signal. Circuit-board analysis software is used to analyze your board layout for crosstalk problems.
Routing Guidelines Figure 7. PCB Ground Layout Around Connectors Connector Connector Pins GND PCB Layer A. Incorrect method B. Correct method A9260-01 6.2 EMI Considerations It is highly recommended that you follow good EMI design practices when designing with the 31154: • To minimize EMI on your PCB, a useful technique is not to extend the power planes to the edge of the board. • Another technique is to surround the perimeter of your PCB layers with a GND trace.
Routing Guidelines 6.3 Power Distribution and Decoupling Ensure that there is ample decoupling to ground for the power planes, to minimize the effects of the switching currents. Inadequate high-frequency decoupling results in intermittent and unreliable behavior. As a general guideline, it is recommended that you use the largest easily available capacitor in the lowest-inductance package. The high-speed decoupling capacitor must be placed as close to the pin as possible, with a short, wide trace.
Routing Guidelines 6.4 Trace Impedance The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b, recommends that all signal layers have a controlled impedance of 57 Ω ±10% for add-in card applications. The characteristic impedance of a signal trace is 60–100 Ω for PCI add-in card applications. Selecting the appropriate board stack-up to minimize impedance variations is very important.
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PCI-X Layout Guidelines PCI-X Layout Guidelines 7 For acceptable signal integrity with bus speeds up to 133 MHz, it is important for the PCB design layout to have controlled impedance. The list below provides general guidelines for routing your PCI bus signals: • Avoid routing signal traces longer than 8". • All clock nets must be on the top layer. • All 32-bit interface signals from the PCI edge fingers must be no longer than 1.5" and no shorter than 0.75".
PCI-X Layout Guidelines 7.1 PCI Clock Layout Guidelines The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, allows a maximum of 0.5 ns clock skew timing for each of the PCI-X frequencies: 66 MHz, 100 MHz, and 133 MHz. • Total length of P_CLK for an add-in card is 2.4"–2.6" • Total length of P_CLK in non-add-in card design is less than 8". A typical PCI-X application requires separate clock point-to-point connections distributed to each PCI device.
PCI-X Layout Guidelines Figure 8. PCI Clock Distribution and Matching Requirements Device 8 Intel 31154 133 MHz PCI Bridge Device 7 Device 6 Device 5 Device 4 Device 3 Device 2 Device 1 Notes: !"# $ $ # %#!& '( # "'!!#" '! ()' # " '* +* "%'", + ! ' # "%' # #! '( # "'))# +'! !& #) # )# ') - !"# * %.
PCI-X Layout Guidelines 7.2 PCI-X Topology Layout Guidelines The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, recommends the following guidelines for the number of loads for your PCI-X designs (Table 13). Any deviation from these maximum values requires close attention to layout with regard to loading and trace lengths. Table 13.
PCI-X Layout Guidelines 7.2.1 Single Slot at 133 MHz Figure 9 shows one of the chipset PCI AD lines connected through the W1 and W12 line segments to a single-slot connector through the W13 line segment to the 31154. This AD line is also used as an IDSEL line from line segment W14 to a resistor through W15 to the PCI connector. The other end of the PCI connector IDSEL line connects through W16 to the 31154 IDSEL line input buffer. Figure 9.
PCI-X Layout Guidelines 7.2.1.1 Intel® 31154 133 MHz PCI Bridge Embedded Application at 133 MHz Figure 10 shows the 31154 application in a stand-alone embedded application. In this application the 31154 is shown driving a single PCI device. Table 15 shows the corresponding wiring lengths to use as a reference. Figure 10. Embedded Intel® 31154 133 MHz PCI Bridge Design 133 MHz PCI-X Layout W2 W1 PCI Agent IDSEL I/O Buffer W4 W3 B3058-01 Table 15.
PCI-X Layout Guidelines 7.2.2 Dual-Slot at 100 MHz Figure 11 shows one of the secondary bridge PCI AD lines branching into two segments with each going through slot connectors to a buffer on an add-in card. Table 16 shows the corresponding wiring lengths to use as a reference. This two-slot design uses a balanced-star topology. Figure 11.
PCI-X Layout Guidelines 7.2.2.1 Embedded Intel® 31154 133 MHz PCI Bridge Application at 100 MHz Figure 12 shows the PCI-X layout for a embedded 133 MHz design. In this application the 31154 is driving three loads. Table 17 shows the corresponding wiring lengths to use as a reference. Figure 12. Embedded Intel® 31154 133 MHz PCI Bridge Design 100 MHz PCI-X Layout W1 W2 W3 PCI Agent 1 I/O Buffer IDSEL W5 W4 W6 PCI Agent 2 W7 PCI Agent 3 B3062-02 Table 17.
PCI-X Layout Guidelines 7.2.3 Quad-Slots at 66 MHz Figure 13 shows one of the bridge secondary AD lines branching to four segments with each segment connecting to a slot connector to a buffer on an add-in card. The first segment representing an upper address line branches to a series resistor to become the IDSEL line for slot 1. Table 18 shows the corresponding wiring lengths to use as a reference. Figure 13.
PCI-X Layout Guidelines Table 18. Wiring Lengths for 66 MHz Quad-Slot (Sheet 2 of 2) Lower AD Bus Segment 50 Minimum Length Upper AD Bus Maximum Length Minimum Length Maximum Length Units W15 0.6 0.6 – – inches W16 1.125 1.125 – – inches W21 0.8 1.2 0.8 1.2 inches W22 0.1 0.5 0.1 0.5 inches W23 0.75 1.5 1.75 2.75 inches W32 0.1 0.5 0.1 0.5 inches W33 0.75 1.5 1.75 2.75 inches W42 0.1 0.5 0.1 0.5 inches W43 0.75 1.5 1.75 2.
PCI-X Layout Guidelines 7.2.3.1 Embedded Intel® 31154 133 MHz PCI Bridge Application at 66 MHz Figure 14 shows an 31154 in a stand-alone embedded application. In this application the 31154 is shown driving four loads. Additional loads might be possible with careful simulation. Table 19 shows the corresponding wiring lengths to use as a reference. Figure 14.
PCI-X Layout Guidelines 7.2.4 PCI-X at 33 MHz The 31154 supports running in an eight-slot PICMG 1.2 style passive backplane environment at 33 MHz. To verify this, simulations were run based on the trace impedance of 57 Ω ± 10%. 7.2.4.1 Embedded PCI-X Specification PICMG 1.2 Overview The Embedded PCI-X (ePCI-X) Specification PICMG 1.2 is a specification supported by the PCI Industrial Computer Manufacturers Group. ePCI-X system host boards (SHBs) are defined in two form factors: full-size and half-size.
PCI-X Layout Guidelines Figure 15 shows an example of this system with dual 64-bit buses with four expansion slots on each bus. The backplane example shows the SHB in an ISA chassis. The SHB slot is in the center of the board. Figure 16 shows the data bus segments for this eight-slot topology, and Table 20 lists the segment lengths for the wiring segments. Figure 17 shows the clock segment lengths and Table 21 lists the clock segments lengths. Figure 15.
PCI-X Layout Guidelines Figure 16. PCI-X Data Bus PICMG 1.2 Style Backplane Intel® 31154 133 MHz PCI Bridge Slot1 Slot2 Slot3 Slot4 Slot5 Slot6 Slot7 Slot8 W1 W2 W3 W4 W5 W6 W7 W8 Device Card Stub Edge Connector W9 W10 W11 W12 W13 W14 W15 Backplane B3331-01 Table 20. Wiring Lengths for PICMG 1.2 Backplane AD Bus Segment 54 Units Minimum Length Maximum Length W1 0.75 2.75 inches W2 0.75 2.75 inches W3 0.75 2.75 inches W4 0.75 2.75 inches W5 0.75 2.
PCI-X Layout Guidelines Figure 17. PCI-X Clock PICMG 1.2 Style Backplane Intel® 31154 133 MHz PCI Bridge Clock Buffer Slot1 SlotN Device S1 WN 39 Ohms Card Stub S2 Edge Connector BN Backplane B3332-01 Table 21. PCI-X Clock Wiring Lengths for PICMG Backplane Clock Point to Point Segment Units Minimum Length Maximum Length S1 0 0.3 inches S2 0.75 2.75 inches WN 0.75 2.75 inches BN 6.5 16.
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Power Considerations 8 Power Considerations 8.1 Analog Power Pins The analog voltage pins S_VCCA and P_VCCA require a low-pass filter. This is implemented by connecting the P_VCCA and S_VCCA pins to a 10 Ω series resistor and 0.01 µF and 4.7 µF (lowESR) capacitors in parallel going to ground. The opposite end of the 10 Ω resistor is connected to the 1.3 V supply. This arrangement is shown in Figure 18 and Figure 19.
Power Considerations 8.2 Power Sequencing When either P_VIO or S_VIO is connected to a power supply other than VCCP, you must perform one of the following steps (listed in order from most favorably recommended to least favorably recommended): 1. Ensure that the P_VIO or S_VIO power comes up before or simultaneously with VCCP, and ensure that the P_VIO or S_VIO power goes down after or simultaneously with VCCP. 2.
Customer Reference Board 9 Customer Reference Board This chapter provides information on the customer reference board based on the Intel® 31154 133 MHz PCI Bridge—the Intel® IQ31154 Customer Reference Board (CRB). Figure 21 shows the block diagram for this CRB. The schematics for this board are provided on the Intel Developer’s website (document number 278839)1. Figure 21.
Customer Reference Board The IQ31154 CRB is implemented on eight layers. These layers are detailed in Table 22. This example is provided as a reference; each individual 31154 application may vary. Table 22. Customer Reference Board Stackup Layers Signal Top layer Signal layer—critical nets (clocks, S/P AD buses) 2nd layer Ground plane 3rd layer Signal layer 4th layer Power plane—(split voltage plane 3.3 and 1.
Debug Connectors and Logic Analyzer Connectivity Debug Connectors and Logic Analyzer Connectivity 10 10.1 Probing PCI-X Signals To ease the probing and debugging of the PCI-X signals, you are recommended to passively probe the PCI-X bus signals with a logic analyzer. This can be done by placing six AMP* Mictor-38 connectors on the board or by probing the bus with an interposer card such as the FuturePlus* Systems* FS2007 that works with an Agilent Technologies* logic analyzer.
Debug Connectors and Logic Analyzer Connectivity Table 23.
Debug Connectors and Logic Analyzer Connectivity Table 24.
Debug Connectors and Logic Analyzer Connectivity Table 25.
Debug Connectors and Logic Analyzer Connectivity Table 26.
Debug Connectors and Logic Analyzer Connectivity Table 27.
Debug Connectors and Logic Analyzer Connectivity Table 28. Logic Analyzer Pod 6 Mictor-38 Pin Number Even Pod Logic Analyzer Channel Number PCI-X Signal Name 5 CLK/16 Unused 7 15 AD63 9 14 AD62 11 13 AD60 13 12 AD59 15 11 AD58 17 10 AD57 19 9 AD56 21 8 AD55 23 7 AD54 25 6 AD53 27 5 AD52 29 4 AD51 31 3 AD50 33 2 AD49 35 1 AD48 37 0 AD48 The recommended placement of the Mictor connectors is at either end of the bus segment.
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Thermal Solutions 11 Thermal Solutions The Intel® 31154 133 MHz PCI Bridge is packaged in a 421-lead PBGA package. The mechanical dimensions for this package are provided in Figure 2, “Intel® 31154 133 MHz PCI Bridge Package” on page 14. Table 29 gives the operational power specifications. Table 29. Operational Power Voltage Maximum Power 3.3 V 2.5 W 1.3 V 0.
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References 12 References 12.1 Related Documents Table 30 lists several books and specifications that are helpful for designing with the Intel® 31154 133 MHz PCI Bridge. Table 30. Design Reference Material Design Reference Material Brian C. Wadell, Transmission Line Design Handbook (Artech House, 1991) K. C. Gupta, et al., Microstrip Lines and Slotlines (Artech House, 1996) Moises Cases, Nam Pham, and Dan Neal, Design, Modeling and Simulation Methodology for High Frequency PCI-X Subsystems, (http://www.
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