Datasheet

Processor Integrated I/O (IIO) Configuration Registers
96 Datasheet, Volume 2
3.2.4.74 ERRCAPHDR—PCI Express* Enhanced Capability Header 
Register – Root Ports
3.2.4.75 UNCERRSTS—Uncorrectable Error Status Register
This register identifies uncorrectable errors detected for PCI Express/DMI port
ERRCAPHDR
Bus: 0 Device: 0 Function: 0 Offset: 148h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 148h
Bus: 0 Device: 2 Function: 0–3 Offset: 148h
Bus: 0 Device: 3 Function: 0–3 Offset: 148h
Bit Attr
Reset
Value
Description
31:20 RO 1D0h
Next Capability Offset
This field points to the next Capability in extended configuration space or is 0 if it
is that last capability.
19:16 RO 1h
Capability Version
Set to 1h for this version of the PCI Express logic
15:0 RO 0001h
PCI Express Extended CAP ID
Assigned for advanced error reporting
UNCERRSTS
Bus: 0 Device: 0 Function: 0 Offset: 14Ch
Bus: 0 Device: 1 Function: 0–1 Offset: 14Ch
Bus: 0 Device: 2 Function: 0–3 Offset: 14Ch
Bus: 0 Device: 3 Function: 0–3 Offset: 14Ch
Bit Attr
Reset
Value
Description
31:22 RV 0h Reserved
21 RW1CS 0b ACS Violation Status
20 RW1CS 0b Received an Unsupported Request
19 RV 0h Reserved
18 RW1CS 0b Malformed TLP Status
17 RW1CS 0b Receiver Buffer Overflow Status
16 RW1CS 0b Unexpected Completion Status
15 RW1CS 0b Completer Abort Status
14 RW1CS 0b Completion Time-out Status
13 RW1CS 0b Flow Control Protocol Error Status
12 RW1CS 0b Poisoned TLP Status
11:6 RV 0h Reserved
5RW1CS0b
Surprise Down Error Status
Note: For non hot-plug removals, this will be logged only when SLTCON[10] is set
to 0.
4RW1CS0bData Link Protocol Error Status
3:0 RV 0h Reserved