Datasheet

Datasheet, Volume 2 95
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Processor Integrated I/O (IIO) Configuration Registers
3.2.4.71 APICLIMIT—APIC Limit Register
3.2.4.72 VSECHDR—PCI Express* Enhanced Capability Header 
Register – DMI2 Mode
3.2.4.73 VSHDR—Vendor Specific Header Register – DMI2 Mode
APICLIMIT
Bus: 0 Device: 0 Function: 0 Offset: 142h
Bus: 0 Device: 1 Function: 0–1 Offset: 142h
Bus: 0 Device: 2 Function: 0–3 Offset: 142h
Bus: 0 Device: 3 Function: 0–3 Offset: 142h
Bit Attr
Reset
Value
Description
15:12 RV 0h Reserved
11:1 RW 000h
Bits 19:9 of the APIC limit
Applies only to root ports.
Bits 31:20 are assumed to be FECh. Bits 8:0 are a don’t care for address decode.
Address decoding to the APIC range is done as:
APICBASE.ADDR[31:8]  A[31:8]  APICLIMIT.ADDR[31:8].
Outbound accesses to the APIC range are claimed by the root port and forwarded
to PCIe, if the range is enabled, even if the MSE bit of the root port is clear or the
root port itself is in D3hot state.
0RV0hReserved
VSECHDR
Bus: 0 Device: 0 Function: 0 Offset: 144h
Bit Attr
Reset
Value
Description
31:20 RO 1D0h
Next Capability Offset
This field points to the next Capability in extended configuration space or is 0 if it
is that last capability.
19:16 RO 1h
Capability Version
Set to 1h for this version of the PCI Express logic
15:0 RO 000Bh
PCI Express Extended CAP ID
Assigned for Vendor Specific Capability
VSHDR
Bus: 0 Device: 0 Function: 0 Offset: 148h
Bit Attr
Reset
Value
Description
31:20 RO 3Ch
VSEC Length
This field points to the next Capability in extended configuration space which is
the ACS capability at 150h.
19:16 RO 1h
VSEC Version
Set to 1h for this version of the PCI Express logic
15:0 RO 4h
VSEC ID
Identifies Intel Vendor Specific Capability for AER on DMI