Datasheet

Processor Integrated I/O (IIO) Configuration Registers
94 Datasheet, Volume 2
3.2.4.69 ACSCTRL—Access Control Services Control Register
3.2.4.70 APICBASE—APIC Base Register
ACSCTRL
Bus: 0 Device: 0 Function: 0 Offset: 116h(PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 116h
Bus: 0 Device: 2 Function: 0–3 Offset: 116h
Bus: 0 Device: 3 Function: 0–3 Offset: 116h
Bit Attr
Reset
Value
Description
15:7 RV 0h Reserved
6RO0b
ACS Direct Translated P2P Enable
Applies only to root ports This is hardwired to 0b as the component does not
implement ACS Direct Translated peer-to-peer.
5RO0b
ACS P2P Egress Control Enable
Applies only to root ports. The component does not implement ACS peer-to-peer
Egress Control and hence this bit should not be used by software.
4RW0b
ACS Upstream Forwarding Enable
Applies only to root ports. When this bit is set, transactions arriving from a root
port that target the same port back down, will be forwarded. Normally such traffic
would be aborted.
Other than this, the bit has no other impact on IIO hardware.
3RW0b
ACS P2P Completion Redirect Enable
Applies only to root ports. Determines when the component redirects peer-to-peer
Completions upstream; applicable only to Read Completions whose Relaxed
Ordering Attribute is clear.
2RW0b
ACS P2P Request Redirect Enable
Applies only to root ports. When this bit is set, transactions arriving from a root
port that target the same port back down, will be forwarded. Normally such traffic
would be aborted.
Other than this, the bit has no other impact on IIO hardware.
1RW0b
ACS Translation Blocking Enable
Applies only to root ports. When set, the component blocks all upstream Memory
Requests whose Address Translation (AT) field is not set to the default value.
0RW0b
ACS Source Validation Enable
Applies only to root ports. When set, the component validates the Bus Number
from the Requester ID of upstream Requests against the secondary / subordinate
Bus Numbers.
APICBASE
Bus: 0 Device: 0 Function: 0 Offset: 140h
Bus: 0 Device: 1 Function: 0–1 Offset: 140h
Bus: 0 Device: 2 Function: 0–3 Offset: 140h
Bus: 0 Device: 3 Function: 0–3 Offset: 140h
Bit Attr
Reset
Value
Description
15:12 RV 0h Reserved
11:1 RW 000h
Bits 19:9 of the APIC base Applies only to root ports.
Bits 31:20 are assumed to be FECh. Bits 8:0 are a don’t care for address decode.
Address decoding to the APIC range is done as:
APICBASE.ADDR[31:8]  A[31:8]  APICLIMIT.ADDR[31:8].
Outbound accesses to the APIC range are claimed by the root port and forwarded
to PCIe, if bit 0 is set, even if the MSE bit of the root port is clear or the root port
itself is in D3hot state.
0RW0h
APIC Range Enable
Enables the decode of the APIC window