Datasheet
Processor Integrated I/O (IIO) Configuration Registers
90 Datasheet, Volume 2
3.2.4.63 PMCSR—Power Management Control and Status Register
This register provides status and control information for PM events in the PCI Express
port of the IIO.
PMCSR
Bus: 0 Device: 0 Function: 0 Offset: E4h
Bus: 0 Device: 1 Function: 0–1 Offset: E4h
Bus: 0 Device: 2 Function: 0–3 Offset: E4h
Bus: 0 Device: 3 Function: 0–3 Offset: E4h
Bit Attr
Reset
Value
Description
31:24 RO 00h
Data
Not relevant for IIO
23 RO 0h
Bus Power/Clock Control Enable
This field is hardwired to 0h as it does not apply to PCI Express.
22 RO 0h
B2/B3 Support
This field is hardwired to 0h as it does not apply to PCI Express.
21:16 RV 0h Reserved
15 RO 0h
PME Status
Applies only to RPs. This bit is hard-wired to read-only 0, since this function does
not support PME# generation from any power state.
This PME Status is a sticky bit. This bit is set, independent of the PMEEN bit
defined below, on an enabled PCI Express hotplug event provided the RP was in
D3hot state. Software clears this bit by writing a 1 when it has been completed.
Refer to PCI Express Base Specification, Revision 3.0 for further details on wake
event generation at a RP
14:13 RO 0h
Data Scale
Not relevant for IIO
12:9 RO 0h
Data Select
Not relevant for IIO
8RO0h
PME Enable
Applies only to RPs.
0 = Disable ability to send PME messages when an event occurs
1 = Enables ability to send PME messages when an event occurs
7:4 RV 0h Reserved
3RW-O 1b
Indicates IIO does not reset its registers when it transitions from D3hot
to D0
2RV0hReserved
1:0 RW 0h
Power State
This 2-bit field is used to determine the current power state of the function and to
set a new power state as well.
00 = D0
01 = D1 (not supported by IIO)
10 = D2 (not supported by IIO)
11 = D3_hot
If Software tries to write 01 or 10 to this field, the power state does not change
from the existing power state (which is either D0 or D3hot) and nor do these bits
1:0 change value.
All devices will respond to only Type 0 configuration transactions when in D3hot
state (RP will not forward Type 1 accesses to the downstream link) and will not
respond to memory/IO transactions (that is, D3hot state is equivalent to MSE/
IOSE bits being clear) as target and will not generate any memory/IO/
configuration transactions as initiator on the primary bus (messages are still
allowed to pass through).