Datasheet

Processor Integrated I/O (IIO) Configuration Registers
88 Datasheet, Volume 2
3.2.4.61 LNKSTS2—PCI Express* Link Status Register 2
LNKSTS2
Bus: 0 Device: 0 Function: 0 Offset: 1C2h (DMI2 MODE)
Bus: 0 Device: 0 Function: 0 Offset: C2h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: C2h
Bus: 0 Device: 2 Function: 0–3 Offset: C2h
Bus: 0 Device: 3 Function: 0–3 Offset: C2h
Bit Attr
Reset
Value
Description
15:6 RV 0h Reserved
5RW1C 0b
Link Equalization Request
This bit is set by hardware to request Link equalization process to be performed
on the link.
4RO-V0b
Equalization Phase 3 Successful
When set to 1b, this indicates that Phase 3 of the Transmitter Equalization
procedure has successfully completed.
3RO-V0b
Equalization Phase 2 Successful
When set to 1b, this indicates that Phase 2 of the Transmitter Equalization
procedure has successfully completed.
2RO-V0b
Equalization Phase 1 Successful
When set to 1b, this indicates that Phase 1 of the Transmitter Equalization
procedure has successfully completed.
1RO-V0b
Equalization Complete
When set to 1b, this indicates that the Transmitter Equalization procedure has
completed.
0RO-V0b
Current De-emphasis Level
When operating at Gen2 speed, this reports the current de-emphasis level. This
field is Unused for Gen1 speeds
1b = -3.5 dB
0b = -6 dB