Datasheet

Processor Integrated I/O (IIO) Configuration Registers
86 Datasheet, Volume 2
3.2.4.59 LNKCAP2—PCI Express* Link Capabilities 2 Register
4RW1b
Completion Timeout Disable
1 = Disables the Completion Timeout mechanism for all NP tx that IIO issues on
the PCIe/DMI link.
0 = Completion timeout is enabled.
Software can change this field while there is active traffic in the root/DMI port.
3:0 RW 0h
Completion Timeout Value on NP Tx that IIO issues on PCIe/DMI
In Devices that support Completion Timeout programmability, this field allows
system software to modify the Completion Timeout range. The following
encodings and corresponding timeout ranges are defined:
0000b = 10 ms to 50 ms
0001b = Reserved (IIO aliases to 0000b)
0010b = Reserved (IIO aliases to 0000b)
0101b = 16 ms to 55 ms
0110b = 65 ms to 210 ms
1001b = 260 ms to 900 ms
1010b = 1 s to 3.5 s
1101b = 4 s to 13 s
1110b = 17 s to 64 s
When software selects 17 s to 64 s range, “CTOCTRL—Completion Timeout Control
Register” on page 111 further controls the timeout value within that range. For all
other ranges selected by the operating system, the timeout value within that
range is fixed in IIO hardware.
Software can change this field while there is active traffic in the root port.
This value will also be used to control PME_TO_ACK Timeout. That is, this field
sets the timeout value for receiving a PME_TO_ACK message after a
PME_TURN_OFF message has been transmitted. The PME_TO_ACK Timeout has
meaning only if bit 6 of “MISCCTRLSTS—Miscellaneous Control and Status
Register” on page 103 register is set to a 1b.
LNKCAP2
Bus: 0 Device: 0 Function: 0 Offset: BCh
Bus: 0 Device: 1 Function: 0–1 Offset: BCh
Bus: 0 Device: 2 Function: 0–3 Offset: BCh
Bus: 0 Device: 3 Function: 0–3 Offset: BCh
Bit Attr
Reset
Value
Description
31:8 RV 0h Reserved
7:1 RO-V 3h
Supported Link Speeds Vector
This field indicates the supported Link speed(s) of the associated Port. For each
bit, a value of 1b indicates that the corresponding Link speed is supported;
otherwise, the Link speed is not supported.
Bit definitions are:
Bit 1 = 2.5 GT/s set in processor
Bit 2 = 5.0 GT/s set in processor
Bit 3 = 8.0 GT/s set in processor unless PCIe 3.0 is disabled in that part
Bits 7:4 = Reserved
The processor supports all speeds, unless PCIe 3.0 is disabled in that part, then
only Gen1 and Gen2 are supported.
0RV0hReserved
DEVCTRL2
Bus: 0 Device: 0 Function: 0 Offset: F8h (DMI2 MODE)
Bus: 0 Device: 0 Function: 0 Offset: B8h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: B8h
Bus: 0 Device: 2 Function: 0–3 Offset: B8h
Bus: 0 Device: 3 Function: 0–3 Offset: B8h
Bit Attr
Reset
Value
Description