Datasheet

Datasheet, Volume 2 85
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Processor Integrated I/O (IIO) Configuration Registers
3.2.4.58 DEVCTRL2—PCI Express* Device Control Register 2
9RW-O 0b
AtomicOp CAS Completer 128-bit Operand Supported
Unsupported
8RW-O 0b
AtomicOp Completer 64-bit Operand Supported
Unsupported
7RW-O 0b
AtomicOp Completer 32-bit Operand Supported
Unsupported
6RO 0b
AtomicOp Routing Supported
peer-to-peer routing of AtomicOp is not supported
5RW-O 1b
Alternative RID InterpretationCapable
This bit is set to 1b indicating Root Port supports this capability.
4RO 1b
Completion Timeout Disable Supported
IIO supports disabling completion timeout
3:0 RO Eh
Completion Timeout Values Supported
This field indicates device support for the optional Completion Timeout program-
mability mechanism. This mechanism allows system software to modify the
Completion Timeout range. Bits are one-hot encoded and set according to the
table below to show timeout value ranges supported. A device that supports the
optional capability of Completion Timeout Programmability must set at least two
bits.Four time values ranges are defined:
Range A = 50 us to 10 ms
Range B = 10 ms to 250 ms
Range C = 250 ms to 4 s
Range D = 4 s to 64 s
Bits are set according to table below to show timeout value ranges supported.
0000b = Completions Timeout programming not supported – values is fixed by
implementation in the range 50 us to 50 ms.
0001b = Range A
0010b = Range B
0011b = Range A & B
0110b = Range B & C
0111b = Range A, B, & C
1110b = Range B, C D
1111b = Range A, B, C & D
All other values are reserved.
IIO supports timeout values up to 10 ms–64 s.
DEVCTRL2
Bus: 0 Device: 0 Function: 0 Offset: F8h (DMI2 MODE)
Bus: 0 Device: 0 Function: 0 Offset: B8h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: B8h
Bus: 0 Device: 2 Function: 0–3 Offset: B8h
Bus: 0 Device: 3 Function: 0–3 Offset: B8h
Bit Attr
Reset
Value
Description
15:6 RV 0h Reserved
5RO 0b
Alternative RID InterpretationEnable
This bit applies only to root ports. When set to 1b, ARI is enabled for the Root
Port. For Device 0 in DMI mode, this bit is ignored.
DEVCAP2
Bus: 0 Device: 0 Function: 0 Offset: B4h
Bus: 0 Device: 1 Function: 0–1 Offset: B4h
Bus: 0 Device: 2 Function: 0–3 Offset: B4h
Bus: 0 Device: 3 Function: 0–3 Offset: B4h
Bit Attr
Reset
Value
Description