Datasheet

Processor Integrated I/O (IIO) Configuration Registers
84 Datasheet, Volume 2
3.2.4.56 ROOTSTS—PCI Express* Root Status Register
3.2.4.57 DEVCAP2—PCI Express* Device Capabilities 2 Register
ROOTSTS
Bus: 0 Device: 0 Function: 0 Offset: B0h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: B0h
Bus: 0 Device: 2 Function: 0–3 Offset: B0h
Bus: 0 Device: 3 Function: 0–3 Offset: B0h
Bit Attr
Reset
Value
Description
31:18 RV 0h Reserved
17 RO-V 0b
PME Pending
This field indicates that another PME is pending when the PME Status bit is set.
When the PME Status bit is cleared by software, the pending PME is delivered by
hardware by setting the PME Status bit again and updating the Requestor ID
appropriately. The PME pending bit is cleared by hardware if no more PMEs are
pending.
16 RW1C 0b
PME Status
This field indicates a PM_PME message (either from the link or internally from
within that root port) was received at the port.
1 = PME was asserted by a requester as indicated by the PME Requester ID field
This bit is cleared by software by writing a 1. The root port itself could be the
source of a PME event when a hot-plug event is observed when the port is in
D3hot state.
15:0 RO-V 0000h
PME Requester ID
This field indicates the PCI requester ID of the last PME requestor. If the root port
itself was the source of the (virtual) PME message, then a RequesterID of
CPUBUSNO0 :DevNo:FunctionNo is logged in this field.
DEVCAP2
Bus: 0 Device: 0 Function: 0 Offset: B4h
Bus: 0 Device: 1 Function: 0–1 Offset: B4h
Bus: 0 Device: 2 Function: 0–3 Offset: B4h
Bus: 0 Device: 3 Function: 0–3 Offset: B4h
Bit Attr
Reset
Value
Description
31:14 RV 0h Reserved
13:12 RW-O 01b
TPH Completer Supported
This field indicates the support for TLP Processing Hints. Processor does not
support the extended TPH header.
00 = TPH and Extended TPH Completer not supported.
01 = TPH Completer supported; Extended TPH Completer not supported.
10 = Reserved.
11 = Both TPH and Extended TPH Completer supported.
11 RW-O 0b
LTR Mechanism Supported
A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR)
mechanism capability.
10 RO 0b
No RO-enabled PR-PR Passing
If this bit is Set, the routing element never carries out the passing permitted by
PCIe ordering rule entry A2b that is associated with the Relaxed Ordering
Attribute field being Set.
This bit applies only for Switches and RCs that support peer to peer traffic
between Root Ports. This bit applies only to Posted Requests being forwarded
through the Switch or RC and does not apply to traffic originating or terminating
within the Switch or RC itself. All Ports on a Switch or RC must report the same
value for this bit. For all other functions, this bit must be 0b.