Datasheet
Datasheet, Volume 2 83
Processor Integrated I/O (IIO) Configuration Registers
3.2.4.55 ROOTCAP—PCI Express* Root Capabilities Register
0RW0b
System Error on Correctable Error Enable
This field controls notifying the internal IIO core error logic of the occurrence of a
correctable error in the device or below its hierarchy. The internal core error logic
of IIO then decides if/how to escalate the error further (pins/message, and so on).
1 = Indicates that an internal core error logic notification should be generated if a
correctable error (ERR_COR) is reported by any of the devices in the
hierarchy associated with and including this port.
0 = No internal core error logic notification should be generated on a correctable
error (ERR_COR) reported by any of the devices in the hierarchy associated
with and including this port.
Generation of system notification on a PCI Express correctable error is orthogonal
to generation of an MSI/INTx interrupt for the same error. Both a system error
and MSI/INTx can be generated on a correctable error or software can chose one
of the two.
Refer to PCI Express Base Specification, Revision 3.0 for details of how this bit is
used in conjunction with other error control bits to generate core logic notification
of error events in a PCI Express port.
Since this register is defined only in PCIe mode for Device#0, this bit will read a 0
in DMI mode. So, to enable core error logic notification on DMI mode correctable
errors, BIOS must set bit 33 of “MISCCTRLSTS—Miscellaneous Control and Status
Register” on page 103 to a 1 (to override this bit) on Device#0 in DMI mode.
ROOTCAP
Bus: 0 Device: 0 Function: 0 Offset: AEh (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: AEh
Bus: 0 Device: 2 Function: 0–3 Offset: AEh
Bus: 0 Device: 3 Function: 0–3 Offset: AEh
Bit Attr
Reset
Value
Description
15:1 RV 0h Reserved
0RO 1b
CRS Software Visibility
This bit, when set, indicates that the Root Port is capable of returning
Configuration Request Retry Status (CRS) Completion Status to software.
Processor supports this capability.
ROOTCON
Bus: 0 Device: 0 Function: 0 Offset: ACh
Bus: 0 Device: 1 Function: 0–1 Offset: ACh
Bus: 0 Device: 2 Function: 0–3 Offset: ACh
Bus: 0 Device: 3 Function: 0–3 Offset: ACh
Bit Attr
Reset
Value
Description