Datasheet

Processor Integrated I/O (IIO) Configuration Registers
82 Datasheet, Volume 2
2RW0b
System Error on Fatal Error Enable
This field enables notifying the internal IIO core error logic of occurrence of an
uncorrectable fatal error at the port or below its hierarchy. The internal core error
logic of IIO then decides if/how to escalate the error further (pins/message etc).
1 = Indicates that an internal IIO core error logic notification should be generated
if a fatal error (ERR_FATAL) is reported by any of the devices in the hierarchy
associated with and including this port.
0 = No internal IIO core error logic notification should be generated on a fatal
error (ERR_FATAL) reported by any of the devices in the hierarchy associated
with and including this port.
Generation of system notification on a PCI Express fatal error is orthogonal to
generation of an MSI/INTx interrupt for the same error. Both a system error and
MSI/INTx can be generated on a fatal error or software can chose one of the two.
Refer to PCI Express Base Specification, Revision 3.0 for details of how this bit is
used in conjunction with other error control bits to generate core logic notification
of error events in a PCI Express port.
Since this register is defined only in PCIe mode for Device 0, this bit will read a 0
in DMI mode. Thus, to enable core error logic notification on DMI mode fatal
errors, BIOS must set bit 35 of “MISCCTRLSTS—Miscellaneous Control and Status
Register” on page 103 to a 1 (to override this bit) on Device 0 in DMI mode.
1RW0b
System Error on Non-Fatal Error Enable
This field enables notifying the internal IIO core error logic of occurrence of an
uncorrectable non-fatal error at the port or below its hierarchy. The internal IIO
core error logic then decides if/how to escalate the error further (pins/message
etc).
1 = Indicates that a internal IIO core error logic notification should be generated
if a non-fatal error (ERR_NONFATAL) is reported by any of the devices in the
hierarchy associated with and including this port.
0 = No internal core error logic notification should be generated on a non-fatal
error (ERR_NONFATAL) reported by any of the devices in the hierarchy
associated with and including this port.
Generation of system notification on a PCI Express non-fatal error is orthogonal to
generation of an MSI/INTx interrupt for the same error. Both a system error and
MSI/INTx can be generated on a non-fatal error or software can chose one of the
two.
Refer to PCI Express Base Specification, Revision 3.0 for details of how this bit is
used in conjunction with other error control bits to generate core logic notification
of error events in a PCI Express port.
Since this register is defined only in PCIe mode for Device#0, this bit will read a 0
in DMI mode. So, to enable core error logic notification on DMI mode non-fatal
errors, BIOS must set bit 34 of “MISCCTRLSTS—Miscellaneous Control and Status
Register” on page 103 to a 1 (to override this bit) on Device#0 in DMI mode.
ROOTCON
Bus: 0 Device: 0 Function: 0 Offset: ACh
Bus: 0 Device: 1 Function: 0–1 Offset: ACh
Bus: 0 Device: 2 Function: 0–3 Offset: ACh
Bus: 0 Device: 3 Function: 0–3 Offset: ACh
Bit Attr
Reset
Value
Description