Datasheet

Datasheet, Volume 2 81
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Processor Integrated I/O (IIO) Configuration Registers
3.2.4.54 ROOTCON—PCI Express* Root Control Register
5RO 0b
MRL Sensor State
This bit reports the status of an MRL sensor if it is implemented.
0 = MRL Closed
1 = MRL Open.
4RW1C0b
Command Completed
This bit is set by IIO when the hot-plug command has completed and the hot-plug
controller is ready to accept a subsequent command. It is subsequently cleared by
software after the field has been read and processed. This bit provides no
assurance that the action corresponding to the command is complete. Any write to
‘PCI Express Slot Control Register (SLTCON)’ (regardless of the port is capable or
enabled for hot-plug) is considered a ‘hot-plug’ command.
If the port is not hot-plug capable or hot-plug enabled, then the hot-plug
command does not trigger any action on the VPP port but the command is still
completed using this bit.
3RW1C0b
Presence Detect Changed
This bit is set by IIO when the value reported in bit 6 is changes. It is
subsequently cleared by software after the field has been read and processed.
2RW1C0b
MRL Sensor Changed
This bit is set if the value reported in bit 5 changes. It is subsequently cleared by
software after the field has been read and processed.
1RW1C0b
Power Fault Detected
This bit is set by IIO when a power fault event is detected by the power controller
(which is reported using the VPP bit stream). It is subsequently cleared by
software after the field has been read and processed.
0RW1C0b
Attention Button Pressed
This bit is set by IIO when the attention button is pressed. It is subsequently
cleared by software after the field has been read and processed.
IIO silently discards the Attention_Button_Pressed message if received from PCI
Express link without updating this bit.
ROOTCON
Bus: 0 Device: 0 Function: 0 Offset: ACh
Bus: 0 Device: 1 Function: 0–1 Offset: ACh
Bus: 0 Device: 2 Function: 0–3 Offset: ACh
Bus: 0 Device: 3 Function: 0–3 Offset: ACh
Bit Attr
Reset
Value
Description
15:5 RV 0h Reserved
4RW0b
CRS software visibility Enable
This bit, when set, enables the Root Port to return Configuration Request Retry
Status (CRS) Completion Status to software. If this bit is 0, retry status cannot be
returned to software.
3RW0b
PME Interrupt Enable
This field controls the generation of MSI interrupts/INTx interrupts for PME
messages.
1 = Enables interrupt generation upon receipt of a PME message
0 = Disables interrupt generation for PME messages
SLTSTS
Bus: 0 Device: 0 Function: 0 Offset: AAh (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: AAh
Bus: 0 Device: 2 Function: 0–3 Offset: AAh
Bus: 0 Device: 3 Function: 0–3 Offset: AAh
Bit Attr
Reset
Value
Description