Datasheet

Processor Integrated I/O (IIO) Configuration Registers
80 Datasheet, Volume 2
3.2.4.53 SLTSTS—PCI Express* Slot Status Register
The PCI Express Slot Status register defines important status information for
operations such as hot-plug and Power Management.
1RW0h
Power Fault Detected Enable
This bit enables the generation of hot-plug interrupts or wake messages using a
power fault event.
0 = Disables generation of hot-plug interrupts or wake messages when a power
fault event happens.
1 = Enables generation of hot-plug interrupts or wake messages when a power
fault event happens.
0RW0h
Attention Button Pressed Enable
This bit enables the generation of hot-plug interrupts or wake messages using an
attention button pressed event.
0 = Disables generation of hot-plug interrupts or wake messages when the
attention button is pressed.
1 = Enables generation of hot-plug interrupts or wake messages when the
attention button is pressed.
SLTCON
Bus: 0 Device: 0 Function: 0 Offset: A8h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: A8h
Bus: 0 Device: 2 Function: 0–3 Offset: A8h
Bus: 0 Device: 3 Function: 0–3 Offset: A8h
Bit Attr
Reset
Value
Description
SLTSTS
Bus: 0 Device: 0 Function: 0 Offset: AAh (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: AAh
Bus: 0 Device: 2 Function: 0–3 Offset: AAh
Bus: 0 Device: 3 Function: 0–3 Offset: AAh
Bit Attr
Reset
Value
Description
15:9 RV 0h Reserved
8RW1C 0b
Data Link Layer State Changed
This bit is set (if it is not already set) when the state of the Data Link Layer Link
Active bit in the Link Status register changes. Software must read Data Link Layer
Active field to determine the link state before initiating configuration cycles to the
hot-plugged device.
7RO0b
Electromechanical Latch Status
When read, this register returns the current state of the Electromechanical
Interlock (the EMILS pin), which has the defined encodings as:
0 = Electromechanical Interlock Disengaged
1 = Electromechanical Interlock Engaged
6RO0b
Presence Detect State
For ports with slots (where the Slot Implemented bit of the PCI Express Capabil-
ities Registers is 1b), this field is the logical OR of the Presence Detect status
determined using an in-band mechanism and sideband Present Detect pins. Refer
to how PCI Express Base Specification, Revision 3.0 for how the inband presence
detect mechanism works (certain states in the LTSSM constitute ‘card present’ and
others do not).
0 = Card/Module slot empty
1 = Card/module Present in slot (powered or unpowered)
For ports with no slots, IIO hardwires this bit to 1b.
Note: The operating system could get confused when it sees an empty PCI
Express root port, that is, ‘no slots + no presence’, since this is now disallowed in
the specification. Thus, BIOS must hide all unused root ports devices in IIO
configuration space, using the DEVHIDE register.