Datasheet

Processor Integrated I/O (IIO) Configuration Registers
78 Datasheet, Volume 2
3.2.4.52 SLTCON—PCI Express* Slot Control Register
Any write to this register will set the Command Completed bit in the SLTSTS register,
ONLY if the VPP enable bit for the port is set. If the port’s VPP enable bit is set (that is,
hot-plug for that slot is enabled), then the required actions on VPP are completed
before the Command Completed bit is set in the SLTSTS register. If the VPP enable bit
for the port is clear, then the write simply updates this register (see individual bit
definitions for details) but the Command Completed bit in the SLTSTS register is not
set.
0RW-O 0b
Attention Button Present
This bit indicates that the Attention Button event signal is routed (from slot or on-
board in the chassis) to the IIO’s hot-plug controller.
0 = indicates that an Attention Button signal is routed to IIO
1 = indicates that an Attention Button is not routed to IIO
BIOS programs this field with a 1 for CEM/Express Module FFs, if the slot is hot-
plug capable.
SLTCAP
Bus: 0 Device: 0 Function: 0 Offset: A4h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: A4h
Bus: 0 Device: 2 Function: 0–3 Offset: A4h
Bus: 0 Device: 3 Function: 0–3 Offset: A4h
Bit Attr
Reset
Value
Description
SLTCON
Bus: 0 Device: 0 Function: 0 Offset: A8h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: A8h
Bus: 0 Device: 2 Function: 0–3 Offset: A8h
Bus: 0 Device: 3 Function: 0–3 Offset: A8h
Bit Attr
Reset
Value
Description
15:13 RV 0h Reserved
12 RWS 0b
Data Link Layer State Changed Enable
When set to 1, this field enables software notification when Data Link Layer Link
Active bit in the “LNKSTS—PCI Express* Link Status Register” on page 75 register
changes state
11 RW 0b
Electromechanical Interlock Control
When software writes either a 1 to this bit, IIO pulses the EMIL pin. Write of 0 has
no effect. This bit always returns a 0 when read. If electromechanical lock is not
implemented, then either a write of 1 or 0 to this register has no effect.
10 RWS 1b
Power Controller Control
If a power controller is implemented, when writes to this field will set the power
state of the slot per the defined encodings. Reads of this field must reflect the
value from the latest write, even if the bcorresponding hot-plug command is not
executed yet at the VPP, unless software issues a write without waiting for the
previous command to complete in which case the read value is undefined.
0 = Power On
1 = Power Off
Note: If the link experiences an unexpected DL_Down condition that is not the
result of a Hot Plug removal, the Processor follows the PCI Express specification
for logging Surprise Link Down. Software is required to set SLTCON[10] to 0
(Power On) in all devices that do not connect to a slot that supports Hot-Plug to
enable logging of this error in that device.
For devices connected to slots supporting Hot-Plug operations, SLTCON[10] usage
to control PWREN# assertion is as described elsewhere.