Datasheet

Processor Integrated I/O (IIO) Configuration Registers
76 Datasheet, Volume 2
3.2.4.51 SLTCAP—PCI Express* Slot Capabilities Register
The Slot Capabilities register identifies the PCI Express specific slot capabilities.
3:0 RO-V 1h
Current Link Speed
This field indicates the negotiated Link speed of the given PCI Express Link.
0001 = 2.5 Gbps
0010 = 5 Gbps
0011 = 8 Gbps (Port 0 does not support this speed)
Others = Reserved
The value in this field is not defined when the link is not up. Software determines
if the link is up or not by reading bit 13 of this register.
LNKSTS
Bus: 0 Device: 0 Function: 0 Offset: 1B2h (DMI2 MODE)
Bus: 0 Device: 0 Function: 0 Offset: A2h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: A2h
Bus: 0 Device: 2 Function: 0–3 Offset: A2h
Bus: 0 Device: 3 Function: 0–3 Offset: A2h
Bit Attr
Reset
Value
Description
SLTCAP
Bus: 0 Device: 0 Function: 0 Offset: A4h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: A4h
Bus: 0 Device: 2 Function: 0–3 Offset: A4h
Bus: 0 Device: 3 Function: 0–3 Offset: A4h
Bit Attr
Reset
Value
Description
31:19 RW-O 0h
Physical Slot Number
This field indicates the physical slot number of the slot connected to the PCI
Express port and is initialized by BIOS.
18 RO 0b
Command Complete Not Capable
Processor is capable of command complete interrupt.
17 RW-O 0b
Electromechanical Interlock Present
This bit, when set, indicates that an Electromechanical Interlock is implemented
on the chassis for this slot and that lock is controlled by bit 11 in Slot Control
register. This field is initialized by BIOS based on the system architecture.
BIOS Note: This capability is not set if the Electromechanical Interlock control is
connected to main slot power control.
This is expected to be used only for Express Module hot-pluggable slots.
16:15 RW-O 0b
Slot Power Limit Scale
This field specifies the scale used for the Slot Power Limit Value and is initialized
by BIOS. IIO uses this field when it sends a Set_Slot_Power_Limit message on PCI
Express. Range of Values:
00 = 1.0x
01 = 0.1x
10 = 0.01x
11 = 0.001x
Writes to this register trigger a Set_Slot_Power_Limit message to be sent.
14:7 RW-O 00h
Slot Power Limit Value
This field specifies the upper limit on power supplied by slot in conjunction with
the Slot Power Limit Scale value defined previously Power limit (in Watts) = SPLS
x SPLV.
This field is initialized by BIOS. IIO uses this field when it sends a
Set_Slot_Power_Limit message on PCI Express.
Writes to this register trigger a Set_Slot_Power_Limit message to be sent.
Design Note: IIO sends the Set_Slot_Power_Limit message on the link at first
link up condition (except on the DMI link operating in DMI mode) without regards
to whether this register and the Slot Power Limit Scale register are programmed
yet by BIOS.