Datasheet
Datasheet, Volume 2 75
Processor Integrated I/O (IIO) Configuration Registers
3.2.4.50 LNKSTS—PCI Express* Link Status Register
The PCI Express Link Status register provides information on the status of the PCI
Express Link such as negotiated width, training, and so forth. The link status register
needs some default values setup by the local host.
LNKSTS
Bus: 0 Device: 0 Function: 0 Offset: 1B2h (DMI2 MODE)
Bus: 0 Device: 0 Function: 0 Offset: A2h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: A2h
Bus: 0 Device: 2 Function: 0–3 Offset: A2h
Bus: 0 Device: 3 Function: 0–3 Offset: A2h
Bit Attr
Reset
Value
Description
15 RW1C 0b
Link Autonomous Bandwidth Status
This bit is set to 1b by hardware to indicate that hardware has autonomously
changed link speed or width, without the port transitioning through DL_Down
status for reasons other than to attempt to correct unreliable link operation. IIO
does not, on its own, change speed or width autonomously for non-reliability
reasons. IIO only sets this bit when it receives a width or speed change indication
from downstream component that is not for link reliability reasons.
14 RW1C 0b
Link Bandwidth Management Status
This bit is set to 1b by hardware to indicate that either of the following has
occurred without the port transitioning through DL_Down status:
• A link retraining initiated by a write of 1b to the Retrain Link bit has completed
• Hardware has autonomously changed link speed or width to attempt to
correct unreliable link operation
Note: IIO also sets this bit when it receives a width or speed change indication
from downstream component that is for link reliability reasons.
13 RO-V 0b
Data Link Layer Link Active
Set to 1b when the Data Link Control and Management State Machine is in the
DL_Active state; 0b otherwise. When this bit is 0b, the transaction layer
associated with the link will abort all transactions that would otherwise be routed
to that link.
12 RW-O 1b
Slot Clock Configuration
This bit indicates whether the processor receives clock from the same xtal that
also provides clock to the device on the other end of the link.
1 = Indicates that same xtal provides clocks to the processor and the slot or
device on other end of the link
0 = Indicates that different xtals provide clocks to the processor and the slot or
device on other end of the link
In general, this field is expected to be set to 1b by BIOS based on board clock
routing, except probably in some NTB usage models. This bit has to be set to 1b
on DMI mode operation on Device 0.
11 RO-V 0b
Link Training
This field indicates the status of an ongoing link training session in the PCI Express
port
0 = LTSSM has exited the recovery/configuration state.
1 = LTSSM is in recovery/configuration state or the Retrain Link was set but
training has not yet begun.
The IIO hardware clears this bit once LTSSM has exited the recovery/configuration
state. Refer to PCI Express Base Specification, Revision 3.0 for details of which
states within the LTSSM would set this bit and which states would clear this bit.
10 RO 0b Reserved
9:4 RO-V 00h
Negotiated Link Width
This field indicates the negotiated width of the given PCI Express link after training
is completed. Only x1, x2, x4, x8, and x16 link width negotiations are possible in
the processor for Device 1-2 and only x1, x2 and x4 on Device 0. A value of 01h in
this field corresponds to a link width of x1, 02h indicates a link width of x2, and so
on, with a value of 10h for a link width of x16.The value in this field is reserved
and could show any value when the link is not up. Software determines if the link
is up or not by reading bit 13 of this register.