Datasheet
Processor Integrated I/O (IIO) Configuration Registers
74 Datasheet, Volume 2
8RO0b
Enable Clock Power Management
Not Applicable to processor
7RW0b
Extended Synch
This bit when set, forces the transmission of additional ordered sets when exiting
L0s and when in recovery. See PCI Express Base Specification, Revision 3.0 for
details.
6RW-V 0b
Common Clock Configuration
Software sets this bit to indicate that this component and the component at the
opposite end of the Link are operating with a common clock source. A value of 0b
indicates that this component and the component at the opposite end of the Link
are operating with separate reference clock sources. Reset Value of this bit is 0b.
Components use this common clock configuration information to report the correct
L0s and L1 Exit Latencies in the NFTS.
The values used come from these registers depending on the value of this bit:
0 = Use NFTS values from CLSPHYCTL3
1 = Use NFTS values from CLSPHYCTL4
5WO0b
Retrain Link
A write of 1 to this bit initiates link retraining in the given PCI Express/DMI port by
directing the LTSSM to the recovery state if the current state is [L0, L0s or L1]. If
the current state is anything other than L0, L0s, L1, then a write to this bit does
nothing. This bit always returns 0 when read. It is permitted to write 1b to this bit
while simultaneously writing modified values to other fields in this register. If the
LTSSM is not already in Recovery or Configuration, the resulting Link training must
use the modified values. If the LTSSM is already in Recovery or Configuration, the
modified values are not required to affect the Link training that is already in
progress.
4RW0b
Link Disable
This field controls whether the link associated with the PCI Express/DMI port is
enabled or disabled. When this bit is a 1, a previously configured link would return
to the ’disabled’ state as defined in the PCI Express Base Specification, Revision
3.0. When this bit is clear, an LTSSM in the ’disabled’ state goes back to the detect
state.
0 = Enables the link associated with the PCI Express port
1 = Disables the link associated with the PCI Express port
3RO0b
Read Completion Boundary
Set to zero to indicate IIO could return read completions at 64B boundaries
2RV0hReserved
1:0 RW-V 00b
Active State Link PM Control
When 01b or 11b, L0s on transmitter is enabled; otherwise, it is disabled. 10 and
11 enables L1 ASPM.
LNKCON
Bus: 0 Device: 0 Function: 0 Offset: 1B0h (DMI2 MODE)
Bus: 0 Device: 0 Function: 0 Offset: A0h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: A0h
Bus: 0 Device: 2 Function: 0–3 Offset: A0h
Bus: 0 Device: 3 Function: 0–3 Offset: A0h
Bit Attr
Reset
Value
Description