Datasheet

Datasheet, Volume 2 73
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Processor Integrated I/O (IIO) Configuration Registers
3.2.4.49 LNKCON—PCI Express* Link Control Register
The PCI Express Link Control register controls the PCI Express Link specific parameters.
The link control register needs some default values setup by the local host.
9:4 RW-O 4h
Maximum Link Width
This field indicates the maximum width of the given PCI Express Link attached to
the port.
000001 = x1
000010 = x2
000100 = x4
001000 = x8
010000 = x16
Others = Reserved
This is left as a RW-O register for BIOS to update based on the platform usage of
the links.
3:0 RW-O 0010b
Maximum Link Speed
This field indicates the maximum link speed of this Port.
0001 = 2.5 Gbps
0010 = 5 Gbps
0011 = 8 Gbps (Port 0 does not support this speed)
Others = Reserved
Processor supports a maximum of 5 Gbps for the DMI port.
LNKCAP
Bus: 0 Device: 0 Function: 0 Offset: 9Ch (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 9Ch
Bus: 0 Device: 2 Function: 0–3 Offset: 9Ch
Bus: 0 Device: 3 Function: 0–3 Offset: 9Ch
Bit Attr
Reset
Value
Description
LNKCON
Bus: 0 Device: 0 Function: 0 Offset: 1B0h (DMI2 MODE)
Bus: 0 Device: 0 Function: 0 Offset: A0h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: A0h
Bus: 0 Device: 2 Function: 0–3 Offset: A0h
Bus: 0 Device: 3 Function: 0–3 Offset: A0h
Bit Attr
Reset
Value
Description
15:12 RV 0h Reserved
11 RW 0b
Link Autonomous Bandwidth Interrupt Enable
For root ports, when set to 1b, this bit enables the generation of an interrupt to
indicate that the Link Autonomous Bandwidth Status bit has been set. For DMI
mode on Device 0, interrupt is not supported and hence this bit is not useful.
Expectation is that BIOS will set bit 27 in Section 3.2.4.86,
“MISCCTRLSTS—Miscellaneous Control and Status Register” on page 103 to notify
the system of autonomous bandwidth change event on that port.
10 RW 0b
Link Bandwidth Management Interrupt Enable
For root ports, when set to 1b, this bit enables the generation of an interrupt to
indicate that the Link Bandwidth Management Status bit has been set. For DMI
mode on Device 0, interrupt is not supported and hence this bit is not useful.
Expectation is that BIOS will set bit 27 inSection 3.2.4.86,
“MISCCTRLSTS—Miscellaneous Control and Status Register” on page 103 to notify
the system of autonomous bandwidth change event on that port.
9RW0b
Hardware Autonomous Width Disable
When Set, this bit disables hardware from changing the Link width for reasons
other than attempting to correct unreliable Link operation by reducing Link width.
IIO does not, by itself, change width for any reason other than reliability. So this
bit only disables such a width change as initiated by the device on the other end of
the link.