Datasheet

Processor Integrated I/O (IIO) Configuration Registers
70 Datasheet, Volume 2
1RW0b
Non Fatal Error Reporting Enable
This bit controls the reporting of non-fatal errors that IIO detects on the PCI
Express/DMI interface.
0 = Reporting of Non Fatal error detected by device is disabled
1 = Reporting of Non Fatal error detected by device is enabled
Refer to PCI Express Base Specification, Revision 3.0 for complete details of how
this bit is used in conjunction with other bits to report errors.
This bit is not used to control the reporting of other internal component
uncorrectable non-fatal errors (at the port unit) in any way.
0RW0b
Correctable Error Reporting Enable
This bit controls the reporting of correctable errors that IIO detects on the PCI
Express/DMI interface.
0 = Reporting of link Correctable error detected by the port is disabled
1 = Reporting of link Correctable error detected by port is enabled
Refer to PCI Express Base Specification, Revision 3.0 for complete details of how
this bit is used in conjunction with other bits to report errors.
This bit is not used to control the reporting of other internal component
correctable errors (at the port unit) in any way.
DEVCTRL
Bus: 0 Device: 0 Function: 0 Offset: F0h (DMI2 MODE)
Bus: 0 Device: 0 Function: 0 Offset: 98h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 98h
Bus: 0 Device: 2 Function: 0–3 Offset: 98h
Bus: 0 Device: 3 Function: 0–3 Offset: 98h
Bit Attr
Reset
Value
Description