Datasheet

Datasheet, Volume 2 69
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Processor Integrated I/O (IIO) Configuration Registers
3.2.4.46 DEVCTRL—PCI Express* Device Control Register
DEVCTRL
Bus: 0 Device: 0 Function: 0 Offset: F0h (DMI2 MODE)
Bus: 0 Device: 0 Function: 0 Offset: 98h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 98h
Bus: 0 Device: 2 Function: 0–3 Offset: 98h
Bus: 0 Device: 3 Function: 0–3 Offset: 98h
Bit Attr
Reset
Value
Description
15 RV 0h Reserved
14:12 RO 000b
Max_Read_Request_Size
PCI Express/DMI ports in the processor do not generate requests greater than
64B and this field is RO.
11 RO 0b
Enable No Snoop
Not applicable to DMI or PCIe root ports since they never set the ‘No Snoop’ bit for
transactions they originate (not forwarded from peer) to PCI Express/DMI. This bit
has no impact on forwarding of NoSnoop attribute on peer requests.
10 RO 0b
Auxiliary Power Management Enable
Not applicable to Processor
9RO 0b
Phantom Functions Enable
Not applicable to IIO since it never uses phantom functions as a requester.
8RO 0h
Extended Tag Field Enable
Not applicable since IIO it never generates any requests on its own that uses tags
7:5. Note though that on peer to peer writes, IIO forwards the tag field along
without modification and tag fields 7:5 could be set and that is not impacted by
this bit.
7:5 RW 000b
Max Payload Size
This field is set by configuration software for the maximum TLP payload size for
the PCI Express port. As a receiver, the IIO must handle TLPs as large as the set
value. As a requester (That is, for requests where IIO’s own RequesterID is used),
it must not generate TLPs exceeding the set value. Permissible values that can be
programmed are indicated by the Max_Payload_Size_Supported in the Device
Capabilities register.
000 = =128B max payload size
001 = 256B max payload size
others = alias to 128B
IIO can receive packets equal to the size set by this field.
IIO generate read completions as large as the value set by this field.
IIO generates memory writes of max 64B.
4RO 0b
Enable Relaxed Ordering
Not applicable to root/DMI ports since they never set relaxed ordering bit as a
requester (this does not include tx forwarded from peer devices). This bit has no
impact on forwarding of relaxed ordering attribute on peer requests.
3RW0b
Unsupported Request Reporting Enable
This bit controls the reporting of unsupported requests that IIO itself detects on
requests its receives from a PCI Express/DMI port.
0 = Reporting of unsupported requests is disabled
1 = Reporting of unsupported requests is enabled.
Refer to PCI Express Base Specification, Revision 3.0 for complete details of how
this bit is used in conjunction with other bits to UR errors.
2RW0b
Fatal Error Reporting Enable
This bit controls the reporting of fatal errors that IIO detects on the PCI Express/
DMI interface.
0 = Reporting of Fatal error detected by device is disabled
1 = Reporting of Fatal error detected by device is enabled
Refer to PCI Express Base Specification, Revision 3.0 for complete details of how
this bit is used in conjunction with other bits to report errors.
This bit is not used to control the reporting of other internal component
uncorrectable fatal errors (at the port unit) in any way.