Datasheet

Processor Integrated I/O (IIO) Configuration Registers
66 Datasheet, Volume 2
3.2.4.41 MSIPENDING—MSI Pending Bit Register
3.2.4.42 PXPCAPID—PCI Express* Capability Identity Register
3.2.4.43 PXPNXTPTR—PCI Express* Next Pointer Register
MSIPENDING
Bus: 0 Device: 0 Function: 0 Offset: 70h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 70h
Bus: 0 Device: 2 Function: 0–3 Offset: 70h
Bus: 0 Device: 3 Function: 0–3 Offset: 70h
Bit Attr
Reset
Value
Description
31:2 RV 0h Reserved
1:0 RO-V 0h
Pending Bits
This field is relevant only when MSI is enabled and used for interrupts generated
by the root port. When MSI is not enabled or used by the root port, this register
always reads a value 0. For each Pending bit that is set, the PCI Express port has
a pending associated message. When only one message is allocated to the root
port by software, only pending bit 0 is set/cleared by hardware and pending bit 1
always reads 0.
Hardware sets this bit when it has an interrupt pending to be sent. This bit
remains set till either the interrupt is sent by hardware or the status bits
associated with the interrupt condition are cleared by software.
PXPCAPID
Bus: 0 Device: 0 Function: 0 Offset: 90h
Bus: 0 Device: 1 Function: 0–1 Offset: 90h
Bus: 0 Device: 2 Function: 0–3 Offset: 90h
Bus: 0 Device: 3 Function: 0–3 Offset: 90h
Bit Attr
Reset
Value
Description
7:0 RO 10h
Capability ID
This field provides the PCI Express capability ID assigned by PCI-SIG.
PXPNXTPTR
Bus: 0 Device: 0 Function: 0 Offset: 91h
Bus: 0 Device: 1 Function: 0–1 Offset: 91h
Bus: 0 Device: 2 Function: 0–3 Offset: 91h
Bus: 0 Device: 3 Function: 0–3 Offset: 91h
Bit Attr
Reset
Value
Description
7:0 RO E0h
Next Ptr
This field is set to the PCI PM capability.