Datasheet

Datasheet, Volume 2 65
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Processor Integrated I/O (IIO) Configuration Registers
3.2.4.38 MSGADR—MSI Address Register
The MSI Address Register (MSIAR) contains the system specific address information to
route MSI interrupts from the root ports and is broken into its constituent fields.
3.2.4.39 MSGDAT—MSI Data Register
3.2.4.40 MSIMSK—MSI Mask Bit Register
MSGADR
Bus: 0 Device: 0 Function: 0 Offset: 64h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 64h
Bus: 0 Device: 2 Function: 0–3 Offset: 64h
Bus: 0 Device: 3 Function: 0–3 Offset: 64h
Bit Attr
Reset
Value
Description
31:20 RW 000h
Address MSB
This field specifies the 12 most significant bits of the 32-bit MSI address. This field
is RW for compatibility reasons only.
19:2 RW 00000h
Address ID
The definition of this field depends on whether interrupt remapping is enabled or
disabled.
1:0 RV 0h Reserved
MSGDAT
Bus: 0 Device: 0 Function: 0 Offset: 68h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 68h
Bus: 0 Device: 2 Function: 0–3 Offset: 68h
Bus: 0 Device: 3 Function: 0–3 Offset: 68h
Bit Attr
Reset
Value
Description
31:16 RV 0000h Reserved
15:0 RW 0000h
Data
The definition of this field depends on whether interrupt remapping is enabled or
disabled.
MSIMSK
Bus: 0 Device: 0 Function: 0 Offset: 6Ch (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 6Ch
Bus: 0 Device: 2 Function: 0–3 Offset: 6Ch
Bus: 0 Device: 3 Function: 0–3 Offset: 6Ch
Bit Attr
Reset
Value
Description
31:2 RV 0h Reserved
1:0 RW 0h
Mask Bits
Relevant only when MSI is enabled and used for interrupts generated by the root
port. For each Mask bit that is set, the PCI Express port is prohibited from sending
the associated message. When only one message is allocated to the root port by
software, only mask bit 0 is relevant and used by hardware.