Datasheet

Processor Integrated I/O (IIO) Configuration Registers
64 Datasheet, Volume 2
3.2.4.37 MSIMSGCTL—MSI Control Register
MSIMSGCTL
Bus: 0 Device: 3 Function: 0 Offset: 62h
Bit Attr
Reset
Value
Description
15:9 RV 0h Reserved
8RO1b
Per-vector Masking Capable
This bit indicates that PCI Express ports support MSI per-vector masking.
7RO0b
Bus 64-bit Address Capable
A PCI Express Endpoint must support the 64-bit Message Address version of the
MSI Capability structure
1 = Function is capable of sending 64-bit message address
0 = Function is not capable of sending 64-bit message address.
6:4 RW 000b
Multiple Message Enable
Applicable only to PCI Express ports. Software writes to this field to indicate the
number of allocated messages, which are aligned to a power of two. When MSI is
enabled, the software will allocate at least one message to the device. A value of
000 indicates 1 message.
000 = 1
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = Reserved
111 = Reserved
3:1 RO 001b
Multiple Message Capable
IOH’s PCI Express port supports 16 messages for all internal events.
000 = 1
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = Reserved
111 = Reserved
0RW0b
MSI Enable
The software sets this bit to select platform-specific interrupts or transmit MSI
messages.
0 = Disables MSI from being generated.
1 = Enables the PCI Express port to use MSI messages for RAS, provided bit 4 in
MISCCTRLSTS is clear and also enables the Express port to use MSI
messages for PM and HP events at the root port provided these individual
events are not enabled for ACPI handling.
Note: Software must disable INTx and MSI-X for this device when using MSI.