Datasheet

Processor Integrated I/O (IIO) Configuration Registers
62 Datasheet, Volume 2
3.2.4.32 SNXTPTR—Subsystem ID Next Pointer Register
3.2.4.33 DMIRCBAR—DMI Root Complex Register Block Base
Address Register
3.2.4.34 MSICAPID—MSI Capability ID Register
SNXTPTR
Bus: 0 Device: 0 Function: 0 Offset: 41h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 41h
Bus: 0 Device: 2 Function: 0–3 Offset: 41h
Bus: 0 Device: 3 Function: 0–3 Offset: 41h
Bit Attr
Reset
Value
Description
7:0 RO 60h
Next Ptr
This field is set to 60h for the next capability list (MSI capability structure) in the
chain.
DMIRCBAR
Bus: 0 Device: 0 Function: 0 Offset: 50h
Bit Attr
Reset
Value
Description
31:12 RW-LB 00000h
DMI Base Address
This field corresponds to bits 32:12 of the base address DMI Root Complex
register space. BIOS will program this register resulting in a base address for a
4 KB block of contiguous memory address space. This register ensures that a
naturally aligned 4KB space is allocated within the first 64 GB of addressable
memory space. System Software uses this base address to program the DMI Root
Complex register set.
This register is kept around on Device 0 even if that port is operating as PCIe port,
to provide flexibility of using the VCs in PCIe mode as well.
11:1 RV 0h Reserved
0RW-LB0b
DMIRCBAR Enable
0 = DMIRCBAR is disabled and does not claim any memory
1 = DMIRCBAR memory mapped accesses are claimed and decoded
Notes:
1. Accesses to registers pointed to by the DMIRCBAR using the message
channel or JTAG mini-port are not gated by this enable bit; that is, accesses
to these registers are honored regardless of the setting of this bit.
2. BIOS sets this bit only when it wishes to update the registers in the
DMIRCBAR. It must clear this bit when it has finished changing values.
MSICAPID
Bus: 0 Device: 0 Function: 0 Offset: 60h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 60h
Bus: 0 Device: 2 Function: 0–3 Offset: 60h
Bus: 0 Device: 3 Function: 0–3 Offset: 60h
Bit Attr
Reset
Value
Description
7:0 RO 05h
Capability ID
Assigned by PCI-SIG for MSI (root ports).