Datasheet

Datasheet, Volume 2 61
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Processor Integrated I/O (IIO) Configuration Registers
3.2.4.31 SCAPID—Subsystem Capability Identity Register
5RO 0b
Master Abort Mode
Not applicable to PCI Express. This bit is hardwired to 0.
4RW0b
VGA 16-bit Decode
This bit enables the virtual PCI-to-PCI bridge to provide 16-bit decoding of VGA 
I/O address precluding the decoding of alias addresses every 1 KB.
0 = Execute 10-bit address decodes on VGA I/O accesses.
1 = Execute 16-bit address decodes on VGA I/O accesses.
Notes:
1. This bit only has meaning if bit 3 of this register is also set to 1, enabling
VGA I/O decoding and forwarding by the bridge.
2. Refer to PCI-PCI Bridge Specification Revision 1.2 for further details of this
bit behavior.
3RW0b
VGA Enable
This bit controls the routing of processor-initiated transactions targeting VGA
compatible I/O and memory address ranges. This bit must only be set for one
peer-to-peer port in the entire system.
Note: When Device 3 Function 0 is in NTB mode, then the Device 3 Function 0
version of this bit must be left at default value. VGA compatible devices are not
supported on the secondary side of the NTB.
2RW0b
ISA Enable
This bit modifies the response by the root port to an I/O access issued by the core
that targets ISA I/O addresses. This applies only to I/O addresses that are
enabled by the IOBASE and IOLIM registers.
1 = The root port will not forward to PCI Express any I/O transactions addressing
the last 768 bytes in each 1 KB block even if the addresses are within the
range defined by the IOBASE and IOLIM registers.
0 = All addresses defined by the IOBASE and IOLIM for core issued I/O
transactions will be mapped to PCI Express.
1RW0b
SERR Response Enable
This bit controls forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL
messages from the PCI Express port to the primary side.
1 = Enables forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL messages.
0 = Disables forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL
Refer to PCI Express Base Specification, Revision 3.0 for details of the myriad
control bits that control error reporting in IIO.
0RW0b
Parity Error Response Enable
This only effect this bit has is on the setting of bit 8 in the SECSTS register.
SCAPID
Bus: 0 Device: 0 Function: 0 Offset: 40h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 40h
Bus: 0 Device: 2 Function: 0–3 Offset: 40h
Bus: 0 Device: 3 Function: 0–3 Offset: 40h
Bit Attr
Reset
Value
Description
7:0 RO 0Dh
Capability ID
Assigned by PCI-SIG for subsystem capability ID
BCTRL
Bus: 0 Device: 0 Function: 0 Offset: 3Eh(PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 3Eh
Bus: 0 Device: 2 Function: 0–3 Offset: 3Eh
Bus: 0 Device: 3 Function: 0–3 Offset: 3Eh
Bit Attr
Reset
Value
Description