Datasheet

Processor Integrated I/O (IIO) Configuration Registers
60 Datasheet, Volume 2
3.2.4.29 INTPIN—Interrupt Pin Register
3.2.4.30 BCTRL—Bridge Control Register
INTPIN
Bus: 0 Device: 0 Function: 0 Offset: 3Dh
Bus: 0 Device: 1 Function: 0–1 Offset: 3Dh
Bus: 0 Device: 2 Function: 0–3 Offset: 3Dh
Bus: 0 Device: 3 Function: 0–3 Offset: 3Dh
Bit Attr
Reset
Value
Description
7:0 RW-O 01h
Interrupt Pin
The only allowed values in this register are 00h and 01h.
BIOS will leave the register at its default value unless it chooses to fully defeature
INTx generation from a root port. For the latter scenario, BIOS will write a value of
00h before the OS takes control. The OS, when it reads this register to be 00h,
understands that the root port does not generate any INTx interrupt. This helps
simplify some of the BIOS ACPI tables relating to interrupts when INTx interrupt
generation from a root port is not enabled in the platform.
When BIOS writes a value of 00h in this register, that in itself does not disable
INTx generation in hardware. Disabling INTx generation in hardware has to be
achieved through the INTx Disable bit in the “PCICMD—PCI Command Register”
register.
IIO hardware does not use this bit for anything.
For DMI mode operation, it is not applicable, since Device 0 does not generate any
INTx interrupts on its own while in DMI mode.
BCTRL
Bus: 0 Device: 0 Function: 0 Offset: 3Eh(PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 3Eh
Bus: 0 Device: 2 Function: 0–3 Offset: 3Eh
Bus: 0 Device: 3 Function: 0–3 Offset: 3Eh
Bit Attr
Reset
Value
Description
15:12 RV 0h Reserved
11 RO 0b
Discard Timer SERR Status
Not applicable to PCI Express. This bit is hardwired to 0.
10 RO 0b
Discard Timer Status
Not applicable to PCI Express. This bit is hardwired to 0.
9RO0b
Secondary Discard Timer
Not applicable to PCI Express. This bit is hardwired to 0.
8RO0b
Primary Discard Timer
Not applicable to PCI Express. This bit is hardwired to 0.
7RO0b
Fast Back-to-Back Enable
Not applicable to PCI Express. This bit is hardwired to 0.
6RW0b
Secondary Bus Reset
1 = Setting this bit triggers a hot reset on the link for the corresponding PCI
Express port and the PCI Express hierarchy domain subordinate to the port.
This sends the LTSSM into the Training (or Link) Control Reset state, which
necessarily implies a reset to the downstream device and all subordinate
devices. The transaction layer corresponding to the port will be emptied by
virtue of the link going down when this bit is set. This means that in the
outbound direction, all posted transactions are dropped and non-posted
transactions are sent a UR response. In the inbound direction, completions
for inbound NP requests are dropped when they arrive. Inbound posted
writes are retired normally.Note also that a secondary bus reset will not reset
the virtual PCI-to-PCI bridge configuration registers of the targeted PCI
Express port.
0 = No reset happens on the PCI Express port.