Datasheet

6 Datasheet, Volume 2
3.2.8.14 DMIESD—DMI Element self Description Register..........................142
3.2.8.15 DMILED—DMI Link Entry Description Register .............................142
3.2.8.16 DMILBA0—DMI Link Address Register ........................................143
3.2.8.17 DMIVC1CdtThrottle—DMI VC1 Credit Throttle Register .................143
3.2.8.18 DMIVCpCdtThrottle—DMI VCp Credit Throttle Register..................143
3.2.8.19 DMIVCmCdtThrottle—DMI VCm Credit Throttle Register................144
3.3 Integrated I/O Core Registers............................................................................145
3.3.1 Configuration Register Maps (Device 5, Function: 0, 2 and 4) .....................145
3.3.2 PCI Configuration Space Registers Common to Device 5.............................155
3.3.2.1 VID—Vendor Identification Register ...........................................155
3.3.2.2 DID—Device Identification Register............................................155
3.3.2.3 PCICMD—PCI Command Register ..............................................155
3.3.2.4 PCISTS—PCI Status Register.....................................................156
3.3.2.5 RID—Revision Identification Register .........................................157
3.3.2.6 CCR—Class Code Register ........................................................157
3.3.2.7 CLSR—Cacheline Size Register..................................................157
3.3.2.8 HDR—Header Type Register......................................................158
3.3.2.9 SVID—Subsystem Vendor ID Register........................................158
3.3.2.10 SID—Subsystem Device ID Register ..........................................158
3.3.2.11 CAPPTR—Capability Pointer Register ..........................................159
3.3.2.12 INTL—Interrupt Line Register....................................................159
3.3.2.13 INTPIN—Interrupt Pin Register..................................................159
3.3.2.14 PXPCAPID—PCI Express* Capability Identity Register...................159
3.3.2.15 PXPNXTPTR—PCI Express* Next Pointer Register.........................160
3.3.2.16 PXPCAP—PCI Express* Capabilities Register................................160
3.3.3 Intel
®
VT-d, Address Mapping, System Management, 
Coherent Interface, Misc Registers..........................................................160
3.3.3.1 HDRTYPECTRL—PCI Header Type Control Register .......................160
3.3.3.2 MMCFG—MMCFG Address Range Register ...................................161
3.3.3.3 TSEG—TSeg Address Range Register .........................................161
3.3.3.4 GENPROTRANGE1_BASE—Generic Protected Memory Range 1 
Base Address Register .............................................................161
3.3.3.5 GENPROTRANGE1_LIMIT—Generic Protected Memory Range 1 
Limit Address Register .............................................................162
3.3.3.6 GENPROTRANGE2_BASE—Generic Protected Memory Range 2 
Base Address Register .............................................................162
3.3.3.7 GENPROTRANGE2_LIMIT—Generic Protected Memory Range 2 
Limit Address Register .............................................................163
3.3.3.8 TOLM—Top of Low Memory Register ..........................................163
3.3.3.9 TOHM—Top of High Memory Register.........................................163
3.3.3.10 NCMEM_BASE—NCMEM Base Register........................................164
3.3.3.11 NCMEM_LIMIT—NCMEM Limit Register .......................................164
3.3.3.12 MENCMEM_BASE—Intel
®
Management Engine (Intel
®
ME) 
Non-coherent Memory Base Address Register..............................164
3.3.3.13 MENCMEM_LIMIT—Intel
®
ME Non-coherent Memory Limit 
Address Register.....................................................................165
3.3.3.14 CPUBUSNO—CPU Internal Bus Numbers Register.........................165
3.3.3.15 LMMIOL—Local MMIO Low Base Register ....................................166
3.3.3.16 LMMIOH_BASE—Local MMIO High Base Register..........................166
3.3.3.17 LMMIOH_LIMIT—Local MMIO High Base Register .........................167
3.3.3.18 GENPROTRANGE0_BASE—Generic Protected Memory Range 0 
Base Address Register .............................................................167
3.3.3.19 GENPROTRANGE0_LIMIT—Generic Protected Memory Range 0 
Limit Address Register .............................................................168
3.3.3.20 CIPCTRL—Coherent Interface Protocol Control Register ................168
3.3.3.21 CIPSTS—Coherent Interface Protocol Status Register...................170
3.3.3.22 CIPDCASAD—Coherent Interface Protocol DCA Source Address 
Decode Register......................................................................170
3.3.3.23 CIPINTRC—Coherent Interface Protocol Interrupt Control Register .171
3.3.3.24 CIPINTRS—Coherent interface Protocol Interrupt Status Register...172
3.3.3.25 VTBAR—Base Address Register for Intel
®
VT-d Registers..............173