Datasheet

Processor Integrated I/O (IIO) Configuration Registers
58 Datasheet, Volume 2
3.2.4.23 PLIMU—Prefetchable Memory Limit (Upper 32 bits) Register
3.2.4.24 SVID—Subsystem Vendor ID Register
PLIMU
Bus: 0 Device: 0 Function: 0 Offset: 2Ch (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 2Ch
Bus: 0 Device: 2 Function: 0–3 Offset: 2Ch
Bus: 0 Device: 3 Function: 0–3 Offset: 2Ch
Bit Attr
Reset
Value
Description
31:0 RW
000000
00h
Prefetchable Upper 32-bit Memory Limit Address
This field corresponds to A[63:32] of the prefetchable memory address range’s
limit address of the PCI Express port. The Prefetchable Memory Base and Memory
Limit registers define a memory mapped I/O prefetchable address range (64-bit
addresses) that is used by the PCI Express bridge to determine when to forward
memory transactions based on the following formula:
PREFETCH_MEMORY_BASE_UPPER:: PREFETCH_MEMORY_BASE  A[63:20] 
 PREFETCH_MEMORY_LIMIT_UPPER::PREFETCH_MEMORY_LIMIT
The upper 12 bits of both the Prefetchable Memory Base and Memory Limit
registers are read/write and correspond to the upper 12 address bits, A[31:20] of
32-bit addresses. The bottom of the defined memory address range will be aligned
to a 1 MB boundary and the top of the defined memory address range will be one
less than a 1 MB boundary.
The bottom 4 bits of both the Prefetchable Memory Base and Prefetchable Memory
Limit registers are read-only, contain the same value, and encode whether or not
the bridge supports 64-bit addresses.
If these four bits have the value 0h, the bridge supports only 32 bit addresses.
If these four bits have the value 1h, the bridge supports 64-bit addresses and the
Prefetchable Base Upper 32 Bits and Prefetchable Limit Upper 32 Bits registers
hold the rest of the 64-bit prefetchable base and limit addresses respectively.
Notes:
1. Setting the prefetchable memory limit less than prefetchable memory base
disables the 64-bit prefetchable memory range altogether.
2. In general the memory base and limit registers will not be programmed by
software without clearing the MSE bit first.
SVID
Bus: 0 Device: 0 Function: 0 Offset: 2Ch ( DMI2 MODE)
Bus: 0 Device: 0 Function: 0 Offset: 44h ( PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 44h
Bus: 0 Device: 2 Function: 0–3 Offset: 44h
Bus: 0 Device: 3 Function: 0–3 Offset: 44h
Bit Attr
Reset
Value
Description
15:0 RW-O 8086h
Subsystem Vendor ID
Assigned by PCI-SIG for the subsystem vendor. This defaults to 8086 but can be
changed by BIOS.