Datasheet

Datasheet, Volume 2 57
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Processor Integrated I/O (IIO) Configuration Registers
3.2.4.20 PBAS—Prefetchable Memory Base Register
3.2.4.21 PLIM—Prefetchable Memory Limit Register
3.2.4.22 PBASU—Prefetchable Memory Base (Upper 32 bits) Register
PBAS
Bus: 0 Device: 0 Function: 0 Offset: 24h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 24h
Bus: 0 Device: 2 Function: 0–3 Offset: 24h
Bus: 0 Device: 3 Function: 0–3 Offset: 24h
Bit Attr
Reset
Value
Description
15:4 RW FFFh
Prefetchable Memory Base Address
This field corresponds to A[31:20] of the prefetchable memory address range’s
base address of the PCI Express port. See also the PLIMU register description.
3:0 RO 1h
Prefetchable Memory Base Address Capability
IIO sets this bit to 01h to indicate 64-bit capability.
PLIM
Bus: 0 Device: 0 Function: 0 Offset: 26h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 26h
Bus: 0 Device: 2 Function: 0–3 Offset: 26h
Bus: 0 Device: 3 Function: 0–3 Offset: 26h
Bit Attr
Reset
Value
Description
15:4 RW 000h
Prefetchable Memory Limit Address
This field corresponds to A[31:20] of the prefetchable memory address range’s
limit address of the PCI Express port. See also the PLIMU register description.
3:0 RO 1h
Prefetchable Memory Limit Address Capability
IIO sets this field to 01h to indicate 64-bit capability.
PBASU
Bus: 0 Device: 0 Function: 0 Offset: 28h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 28h
Bus: 0 Device: 2 Function: 0–3 Offset: 28h
Bus: 0 Device: 3 Function: 0–3 Offset: 28h
Bit Attr
Reset
Value
Description
31:0 RW FFFFFFFFh
Prefetchable Upper 32-bit Memory Base Address
This field corresponds to A[63:32] of the prefetchable memory address range’s
base address of the PCI Express port. See the PLIMU register description.